Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Yao Jen Lee; Fu Ju Hou; Shang Shiun Chuang; Fu Kuo Hsueh; Kuo Hsing Kao; Po Jung Sung; Wei You Yuan; Jay Yi Yao; Yu Chi Lu; Kun Lin Lin; Chien Ting Wu; Hisu Chih Chen; Bo Yuan Chen; Guo Wei Huang; Henry J.H. Chen; Jiun Yun Li; Yi-ming Li; Seiji Samukawa; Tien Sheng Chao; Tseung Yuen Tseng; Wen Fa Wu; Tuo Hung Hou; Wen Kuan Yeh

doi:10.1109/IEDM.2015.7409701

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Yao Jen Lee
, Fu Ju Hou
, Shang Shiun Chuang
, Fu Kuo Hsueh
, Kuo Hsing Kao
, Po Jung Sung
, Wei You Yuan
, Jay Yi Yao
, Yu Chi Lu
, Kun Lin Lin
, Chien Ting Wu
, Hisu Chih Chen
, Bo Yuan Chen
, Guo Wei Huang
, Henry J.H. Chen
, Jiun Yun Li
, Yi-ming Li
, Seiji Samukawa
, Tien Sheng Chao
, Tseung Yuen Tseng

Wen Fa Wu, Tuo Hung Hou, Wen Kuan Yeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

17 Scopus citations

Abstract

We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I_on/I_off ratio exceeding 108, the highest ever reported for Ge-based pFETs.

Original language	English
Title of host publication	2015 IEEE International Electron Devices Meeting, IEDM 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	15.1.1-15.1.4
Number of pages	4
ISBN (Electronic)	9781467398930
DOIs	https://doi.org/10.1109/IEDM.2015.7409701
State	Published - 7 Dec 2015
Event	61st IEEE International Electron Devices Meeting, IEDM 2015 - Washington, United States Duration: 7 Dec 2015 → 9 Dec 2015

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2016-February
ISSN (Print)	0163-1918

Conference

Conference	61st IEEE International Electron Devices Meeting, IEDM 2015
Country/Territory	United States
City	Washington
Period	7/12/15 → 9/12/15

Access to Document

10.1109/IEDM.2015.7409701

Cite this

Lee, Y. J., Hou, F. J., Chuang, S. S., Hsueh, F. K., Kao, K. H., Sung, P. J., Yuan, W. Y., Yao, J. Y., Lu, Y. C., Lin, K. L., Wu, C. T., Chen, H. C., Chen, B. Y., Huang, G. W., Chen, H. J. H., Li, J. Y., Li, Y., Samukawa, S., Chao, T. S., ... Yeh, W. K. (2015). Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology. In 2015 IEEE International Electron Devices Meeting, IEDM 2015 (pp. 15.1.1-15.1.4). Article 7409701 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2015.7409701

Lee, Yao Jen ; Hou, Fu Ju ; Chuang, Shang Shiun et al. / Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology. 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 15.1.1-15.1.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{f62a1f2b6beb4eacbecc291937b2c9ee,

title = "Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four \{111\} facets by dry etch technology",

abstract = "We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four \{111\} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the \{111\} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs.",

author = "Lee, \{Yao Jen\} and Hou, \{Fu Ju\} and Chuang, \{Shang Shiun\} and Hsueh, \{Fu Kuo\} and Kao, \{Kuo Hsing\} and Sung, \{Po Jung\} and Yuan, \{Wei You\} and Yao, \{Jay Yi\} and Lu, \{Yu Chi\} and Lin, \{Kun Lin\} and Wu, \{Chien Ting\} and Chen, \{Hisu Chih\} and Chen, \{Bo Yuan\} and Huang, \{Guo Wei\} and Chen, \{Henry J.H.\} and Li, \{Jiun Yun\} and Yi-ming Li and Seiji Samukawa and Chao, \{Tien Sheng\} and Tseng, \{Tseung Yuen\} and Wu, \{Wen Fa\} and Hou, \{Tuo Hung\} and Yeh, \{Wen Kuan\}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 61st IEEE International Electron Devices Meeting, IEDM 2015 ; Conference date: 07-12-2015 Through 09-12-2015",

year = "2015",

month = dec,

day = "7",

doi = "10.1109/IEDM.2015.7409701",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "15.1.1--15.1.4",

booktitle = "2015 IEEE International Electron Devices Meeting, IEDM 2015",

address = "美國",

}

Lee, YJ, Hou, FJ, Chuang, SS, Hsueh, FK, Kao, KH, Sung, PJ, Yuan, WY, Yao, JY, Lu, YC, Lin, KL, Wu, CT, Chen, HC, Chen, BY, Huang, GW, Chen, HJH, Li, JY, Li, Y, Samukawa, S, Chao, TS, Tseng, TY, Wu, WF, Hou, TH & Yeh, WK 2015, Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology. in 2015 IEEE International Electron Devices Meeting, IEDM 2015., 7409701, Technical Digest - International Electron Devices Meeting, IEDM, vol. 2016-February, Institute of Electrical and Electronics Engineers Inc., pp. 15.1.1-15.1.4, 61st IEEE International Electron Devices Meeting, IEDM 2015, Washington, United States, 7/12/15. https://doi.org/10.1109/IEDM.2015.7409701

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology. / Lee, Yao Jen; Hou, Fu Ju; Chuang, Shang Shiun et al.
2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 15.1.1-15.1.4 7409701 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2016-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

AU - Lee, Yao Jen

AU - Hou, Fu Ju

AU - Chuang, Shang Shiun

AU - Hsueh, Fu Kuo

AU - Kao, Kuo Hsing

AU - Sung, Po Jung

AU - Yuan, Wei You

AU - Yao, Jay Yi

AU - Lu, Yu Chi

AU - Lin, Kun Lin

AU - Wu, Chien Ting

AU - Chen, Hisu Chih

AU - Chen, Bo Yuan

AU - Huang, Guo Wei

AU - Chen, Henry J.H.

AU - Li, Jiun Yun

AU - Li, Yi-ming

AU - Samukawa, Seiji

AU - Chao, Tien Sheng

AU - Tseng, Tseung Yuen

AU - Wu, Wen Fa

AU - Hou, Tuo Hung

AU - Yeh, Wen Kuan

PY - 2015/12/7

Y1 - 2015/12/7

N2 - We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs.

AB - We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge09Si01 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an Ion/Ioff ratio exceeding 108, the highest ever reported for Ge-based pFETs.

UR - https://www.scopus.com/pages/publications/84964031558

U2 - 10.1109/IEDM.2015.7409701

DO - 10.1109/IEDM.2015.7409701

M3 - Conference contribution

AN - SCOPUS:84964031558

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 15.1.1-15.1.4

BT - 2015 IEEE International Electron Devices Meeting, IEDM 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 61st IEEE International Electron Devices Meeting, IEDM 2015

Y2 - 7 December 2015 through 9 December 2015

ER -

Lee YJ, Hou FJ, Chuang SS, Hsueh FK, Kao KH, Sung PJ et al. Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology. In 2015 IEEE International Electron Devices Meeting, IEDM 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 15.1.1-15.1.4. 7409701. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2015.7409701

Diamond-shaped Ge and Ge0.9Si0.1 gate-all-around nanowire FETs with four {111} facets by dry etch technology

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this