Device trends and implications on circuit design in advanced CMOS technologies

C. H. Diaz*, K. H. Fung, Y. K. Leung, C. C. Wu, C. P. Chao, G. J. Chern, W. Lin, C. Lee, F. S. Lai, M. C. Chang, Y. C. Sun

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

To conciliate scaling-driven fundamental material limitations with industry evolution requirements, flexible CMOS technologies and tighter interaction between process development and circuit/system design are needed to efficiently realize Systems on a Chip (SoC). This paper discusses issues associated with power supply scaling, performance-leakage power optimization including dynamic body / well bias, gate dielectric scaling, mobility enhancement by strained-Si, SRAM process and design interactions, digital and analog device tradeoffs, and HV I/O considerations in advanced CMOS technologies.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2005 Custom Integrated Circuits Conference
Pages670-675
Number of pages6
DOIs
StatePublished - 2005
EventIEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States
Duration: 18 Sep 200521 Sep 2005

Publication series

NameProceedings of the Custom Integrated Circuits Conference
Volume2005
ISSN (Print)0886-5930

Conference

ConferenceIEEE 2005 Custom Integrated Circuits Conference
Country/TerritoryUnited States
CitySan Jose, CA
Period18/09/0521/09/05

Fingerprint

Dive into the research topics of 'Device trends and implications on circuit design in advanced CMOS technologies'. Together they form a unique fingerprint.

Cite this