TY - GEN
T1 - Device structural effects, spice modeling and circuit evaluation for negative-capacitance fets
AU - Su, Pin
AU - You, Wei Xiang
PY - 2019/4
Y1 - 2019/4
N2 - Employing a hafnium-oxide based ferroelectric compatible with present CMOS gate stack, the negative-capacitance FET (NCFET) [1] has garnered substantial interest as it may enable the supply-voltage/power scaling of logic transistors [2]. Several NCFETs, with 2D (Fig. 1) or short-channel FinFET structures, have been experimentally demonstrated with negligible hysteresis (see, e.g., [3] [4]). With its steep slope and similar current transport mechanism to the MOSFET, the NCFET has become a promising beyond-CMOS device candidate.
AB - Employing a hafnium-oxide based ferroelectric compatible with present CMOS gate stack, the negative-capacitance FET (NCFET) [1] has garnered substantial interest as it may enable the supply-voltage/power scaling of logic transistors [2]. Several NCFETs, with 2D (Fig. 1) or short-channel FinFET structures, have been experimentally demonstrated with negligible hysteresis (see, e.g., [3] [4]). With its steep slope and similar current transport mechanism to the MOSFET, the NCFET has become a promising beyond-CMOS device candidate.
UR - http://www.scopus.com/inward/record.url?scp=85072124687&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA.2019.8804708
DO - 10.1109/VLSI-TSA.2019.8804708
M3 - Conference contribution
AN - SCOPUS:85072124687
T3 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
BT - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2019
Y2 - 22 April 2019 through 25 April 2019
ER -