Device Performance of 2D Layered Material Transistors and Their Challenges: A Theoretical Study

Gengchiau Liang*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In this work, we will show the details of device performance of FETs based on black phosphorus and compared to Si UTB structures. Furthermore, we also report the ultimate voltage scalability of double gate ultra-thin body FETs employing materials ranging from group IV, III-V to 2-dimensional (2D) materials based on ITRS for high performance and low operating power applications. We will discuss the potentials using these 2D layered materials in FETs and their challenges.

Original languageEnglish
Title of host publication2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages239-241
Number of pages3
ISBN (Print)9781538637111
DOIs
StatePublished - 26 Jul 2018
Event2nd IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Kobe, Japan
Duration: 13 Mar 201816 Mar 2018

Publication series

Name2018 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018 - Proceedings

Conference

Conference2nd IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018
Country/TerritoryJapan
CityKobe
Period13/03/1816/03/18

Keywords

  • MOSFET and 2D materials

Fingerprint

Dive into the research topics of 'Device Performance of 2D Layered Material Transistors and Their Challenges: A Theoretical Study'. Together they form a unique fingerprint.

Cite this