Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits

Olga Syshchyk; Thibault Cosnier; Zheng Hong Huang; Deepthi Cingu; Dirk Wellekens; Anurag Vohra; Karen Geens; Pavan Vudumula; Urmimala Chatterjee; Stefaan Decoutere; Tian Li Wu; Benoit Bakeroot

doi:10.1109/ESSDERC55479.2022.9947150

Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits

Olga Syshchyk
, Thibault Cosnier
, Zheng Hong Huang
, Deepthi Cingu
, Dirk Wellekens
, Anurag Vohra
, Karen Geens
, Pavan Vudumula
, Urmimala Chatterjee
, Stefaan Decoutere
, Tian Li Wu
, Benoit Bakeroot

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

The device performance of monolithically integrated power Schottky barrier diodes (SBDs) and depletion-mode (D-mode) MIS HEMTs is studied in relation to the thickness of the gate dielectric, the gate-edge termination (GET) layer and AlGaN barrier. Special attention is paid to the turn-on voltage (VTON), ON-resistance (RON), device dispersion, leakage current and breakdown voltage (VBD) of SBDs and D-mode MIS-HEMTs. Based on the current design, SBDs show the lowest dynamic RON for devices with 7.5-9.5 nm AlGaN barrier thickness and 25-35 nm GET thicknesses. The best performance of the D-mode MIS-HEMTs is observed for devices with 5.5 nm AlGaN barrier thickness and 45 nm gate dielectric thickness.

Original language	English
Title of host publication	ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings
Publisher	Editions Frontieres
Pages	245-248
Number of pages	4
ISBN (Electronic)	9781665484978
DOIs	https://doi.org/10.1109/ESSDERC55479.2022.9947150
State	Published - 2022
Event	52nd IEEE European Solid-State Device Research Conference, ESSDERC 2022 - Virtual, Online, Italy Duration: 19 Sep 2022 → 22 Sep 2022

Publication series

Name	European Solid-State Device Research Conference
Volume	2022-September
ISSN (Print)	1930-8876

Conference

Conference	52nd IEEE European Solid-State Device Research Conference, ESSDERC 2022
Country/Territory	Italy
City	Virtual, Online
Period	19/09/22 → 22/09/22

Keywords

GaN
GaN-ICs
Schottky barrier diodes
depletion mode HEMT
enhancement mode HEMT
monolithic integration

Access to Document

10.1109/ESSDERC55479.2022.9947150

Cite this

Syshchyk, O., Cosnier, T., Huang, Z. H., Cingu, D., Wellekens, D., Vohra, A., Geens, K., Vudumula, P., Chatterjee, U., Decoutere, S., Wu, T. L., & Bakeroot, B. (2022). Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits. In ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings (pp. 245-248). (European Solid-State Device Research Conference; Vol. 2022-September). Editions Frontieres. https://doi.org/10.1109/ESSDERC55479.2022.9947150

@inproceedings{48b42ae5ea674bafa8b7ced9fe38d8a1,

title = "Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits",

abstract = "The device performance of monolithically integrated power Schottky barrier diodes (SBDs) and depletion-mode (D-mode) MIS HEMTs is studied in relation to the thickness of the gate dielectric, the gate-edge termination (GET) layer and AlGaN barrier. Special attention is paid to the turn-on voltage (VTON), ON-resistance (RON), device dispersion, leakage current and breakdown voltage (VBD) of SBDs and D-mode MIS-HEMTs. Based on the current design, SBDs show the lowest dynamic RON for devices with 7.5-9.5 nm AlGaN barrier thickness and 25-35 nm GET thicknesses. The best performance of the D-mode MIS-HEMTs is observed for devices with 5.5 nm AlGaN barrier thickness and 45 nm gate dielectric thickness.",

keywords = "GaN, GaN-ICs, Schottky barrier diodes, depletion mode HEMT, enhancement mode HEMT, monolithic integration",

author = "Olga Syshchyk and Thibault Cosnier and Huang, \{Zheng Hong\} and Deepthi Cingu and Dirk Wellekens and Anurag Vohra and Karen Geens and Pavan Vudumula and Urmimala Chatterjee and Stefaan Decoutere and Wu, \{Tian Li\} and Benoit Bakeroot",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 52nd IEEE European Solid-State Device Research Conference, ESSDERC 2022 ; Conference date: 19-09-2022 Through 22-09-2022",

year = "2022",

doi = "10.1109/ESSDERC55479.2022.9947150",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "Editions Frontieres",

pages = "245--248",

booktitle = "ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings",

}

Syshchyk, O, Cosnier, T, Huang, ZH, Cingu, D, Wellekens, D, Vohra, A, Geens, K, Vudumula, P, Chatterjee, U, Decoutere, S, Wu, TL & Bakeroot, B 2022, Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits. in ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings. European Solid-State Device Research Conference, vol. 2022-September, Editions Frontieres, pp. 245-248, 52nd IEEE European Solid-State Device Research Conference, ESSDERC 2022, Virtual, Online, Italy, 19/09/22. https://doi.org/10.1109/ESSDERC55479.2022.9947150

Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits. / Syshchyk, Olga; Cosnier, Thibault; Huang, Zheng Hong et al.
ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings. Editions Frontieres, 2022. p. 245-248 (European Solid-State Device Research Conference; Vol. 2022-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits

AU - Syshchyk, Olga

AU - Cosnier, Thibault

AU - Huang, Zheng Hong

AU - Cingu, Deepthi

AU - Wellekens, Dirk

AU - Vohra, Anurag

AU - Geens, Karen

AU - Vudumula, Pavan

AU - Chatterjee, Urmimala

AU - Decoutere, Stefaan

AU - Wu, Tian Li

AU - Bakeroot, Benoit

PY - 2022

Y1 - 2022

N2 - The device performance of monolithically integrated power Schottky barrier diodes (SBDs) and depletion-mode (D-mode) MIS HEMTs is studied in relation to the thickness of the gate dielectric, the gate-edge termination (GET) layer and AlGaN barrier. Special attention is paid to the turn-on voltage (VTON), ON-resistance (RON), device dispersion, leakage current and breakdown voltage (VBD) of SBDs and D-mode MIS-HEMTs. Based on the current design, SBDs show the lowest dynamic RON for devices with 7.5-9.5 nm AlGaN barrier thickness and 25-35 nm GET thicknesses. The best performance of the D-mode MIS-HEMTs is observed for devices with 5.5 nm AlGaN barrier thickness and 45 nm gate dielectric thickness.

AB - The device performance of monolithically integrated power Schottky barrier diodes (SBDs) and depletion-mode (D-mode) MIS HEMTs is studied in relation to the thickness of the gate dielectric, the gate-edge termination (GET) layer and AlGaN barrier. Special attention is paid to the turn-on voltage (VTON), ON-resistance (RON), device dispersion, leakage current and breakdown voltage (VBD) of SBDs and D-mode MIS-HEMTs. Based on the current design, SBDs show the lowest dynamic RON for devices with 7.5-9.5 nm AlGaN barrier thickness and 25-35 nm GET thicknesses. The best performance of the D-mode MIS-HEMTs is observed for devices with 5.5 nm AlGaN barrier thickness and 45 nm gate dielectric thickness.

KW - GaN

KW - GaN-ICs

KW - Schottky barrier diodes

KW - depletion mode HEMT

KW - enhancement mode HEMT

KW - monolithic integration

UR - https://www.scopus.com/pages/publications/85142717378

U2 - 10.1109/ESSDERC55479.2022.9947150

DO - 10.1109/ESSDERC55479.2022.9947150

M3 - Conference contribution

AN - SCOPUS:85142717378

T3 - European Solid-State Device Research Conference

SP - 245

EP - 248

BT - ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings

PB - Editions Frontieres

T2 - 52nd IEEE European Solid-State Device Research Conference, ESSDERC 2022

Y2 - 19 September 2022 through 22 September 2022

ER -

Syshchyk O, Cosnier T, Huang ZH, Cingu D, Wellekens D, Vohra A et al. Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits. In ESSDERC 2022 - IEEE 52nd European Solid-State Device Research Conference, Proceedings. Editions Frontieres. 2022. p. 245-248. (European Solid-State Device Research Conference). doi: 10.1109/ESSDERC55479.2022.9947150

Device optimization for 200V GaN-on-SOI Platform for Monolithicly Integrated Power Circuits

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Keywords

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