Device isolation process for 4H-SiC CMOS ICs

Bing Yue Tsui*, Ya Ru Jhuang, Jian Hao Lin, Yi Ting Huang, Te Kai Tsai, Kai Ti Hsu, Yi Han Su, Yong Fen Hsieh

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

SiC CMOS ICs attract more and more attention recently. Semi-recessed isolation is one of the key processes for sub-micron ICs. In this paper, LOCal Oxidation of SiC (LOCOSiC) process is reviewed. The growth process and shape control of the field oxide are discussed. The influence of LOCOSiC isolation on gate oxide reliability, junction leakage current, and isolation capability are also presented.

Original languageEnglish
Title of host publication6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages238-240
Number of pages3
ISBN (Electronic)9781665421775
DOIs
StatePublished - 2022
Event6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022 - Virtual, Online, Japan
Duration: 6 Mar 20229 Mar 2022

Publication series

Name6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022

Conference

Conference6th IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2022
Country/TerritoryJapan
CityVirtual, Online
Period6/03/229/03/22

Keywords

  • CMOS
  • ICs and Isolation
  • SiC

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