Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors

Wei Xiang You; Pin Su

doi:10.1109/EDTM.2017.7947540

Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors

Wei Xiang You, Pin Su

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this work, with the aid of an analytical and scalable model, we explore the design space for negative-capacitance (NC) FETs with a 2D semiconducting transition-metal-dichalcogenide (TMD) channel with emphasis on the impact of back-gate biasing. Our study indicates that, to mitigate the conflict between subthreshold swing (SS) and hysteresis and to maximize the design space for the NC-TMDFET, a thin buried oxide (BOX) and an adequate reverse back-gate bias can be applied to achieve the optimum design.

Original language	English
Title of host publication	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	136-137
Number of pages	2
ISBN (Electronic)	9781509046591
DOIs	https://doi.org/10.1109/EDTM.2017.7947540
State	Published - 13 Jun 2017
Event	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Toyama, Japan Duration: 28 Feb 2017 → 2 Mar 2017

Publication series

Name	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings

Conference

Conference	2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017
Country/Territory	Japan
City	Toyama
Period	28/02/17 → 2/03/17

Keywords

2D material
Negative-capacitance FET
transition-metal-dichalcogenide

Access to Document

10.1109/EDTM.2017.7947540

Cite this

You, W. X., & Su, P. (2017). Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors. In 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings (pp. 136-137). Article 7947540 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2017.7947540

You, Wei Xiang ; Su, Pin. / Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors. 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 136-137 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings).

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abstract = "In this work, with the aid of an analytical and scalable model, we explore the design space for negative-capacitance (NC) FETs with a 2D semiconducting transition-metal-dichalcogenide (TMD) channel with emphasis on the impact of back-gate biasing. Our study indicates that, to mitigate the conflict between subthreshold swing (SS) and hysteresis and to maximize the design space for the NC-TMDFET, a thin buried oxide (BOX) and an adequate reverse back-gate bias can be applied to achieve the optimum design.",

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author = "You, {Wei Xiang} and Pin Su",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 ; Conference date: 28-02-2017 Through 02-03-2017",

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You, WX & Su, P 2017, Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors. in 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings., 7947540, 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 136-137, 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017, Toyama, Japan, 28/02/17. https://doi.org/10.1109/EDTM.2017.7947540

Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors. / You, Wei Xiang; Su, Pin.
2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 136-137 7947540 (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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You WX, Su P. Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors. In 2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. p. 136-137. 7947540. (2017 IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2017 - Proceedings). doi: 10.1109/EDTM.2017.7947540

Design space exploration considering back-gate biasing effects for negative-capacitance transition-metal-dichalcogenide (TMD) field-effect transistors

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Keywords

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