Design, Process, and Characterization of Complementary Metal-Oxide-Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC

Chia Lung Hung*, Bing Yue Tsui, Te Kai Tsai, Li Jung Lin, Yu Xin Wen

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

In this study, the performance of complementary metal oxide semiconductor (MOS) circuits fabricated on SiC substrates was investigated by designing several digital and analog circuits, and a unique process flow was developed to integrate n-type MOS (NMOS) and p-type MOS (PMOS) transistors with low and high threshold voltages (Vth) into a single chip. A detailed process flow with local oxidation of SiC isolation and a dual gate oxide with a compromised gate dielectric are presented. The performance of NMOS field-effect transistors (FETs) and PMOSFETs with low and high Vth were characterized in detail. Lateral MOS capacitors were also fabricated in the same chip to explore the characteristics of the gate dielectric. Several common logic gate components were fabricated and tested at elevated temperatures to demonstrate the normal function of these elements in a digital circuit. Static random-access memory (SRAM) cells were designed and optimized through simulation. Characterizations of all the circuit blocks are presented to demonstrate the capability of these circuits in harsh environments.

Original languageEnglish
Article number045001
JournalECS Journal of Solid State Science and Technology
Volume11
Issue number4
DOIs
StatePublished - Apr 2022

Keywords

  • complementary metal-oxide-semiconductor (CMOS)
  • compromised gate dielectric
  • integrated circuit (IC)
  • local oxidation of SiC (LOCOSiC) isolation
  • SiC
  • static random-access memory (SRAM)

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