Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

Ming-Dou Ker; T. Y. Chen

doi:10.1109/ISCAS.2001.922348

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

Ming-Dou Ker^*, T. Y. Chen

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original ∼200V to become ≥ 3kV.

Original language	English
Pages (from-to)	IV758-IV761
Journal	Materials Research Society Symposium - Proceedings
Volume	626
DOIs	https://doi.org/10.1109/ISCAS.2001.922348
State	Published - 2001
Event	Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States Duration: 24 Apr 2000 → 27 Apr 2000

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10.1109/ISCAS.2001.922348

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title = "Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes",

abstract = "A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original ∼200V to become ≥ 3kV.",

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AU - Ker, Ming-Dou

AU - Chen, T. Y.

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N2 - A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original ∼200V to become ≥ 3kV.

AB - A novel power-rail ESD clamp circuit design by using stacked polysilicon diodes to trigger ESD protection device is proposed to achieve excellent on-chip ESD protection. Design methodology of this novel ESD clamp circuit has been derived in detail. Some controlled factors in the novel ESD clamp circuit can be exactly calculated to design a suitable ESD clamp circuit for different power supply applications. By adding this efficient power-rail ESD clamp circuit, the HBM ESD level of a CMOS IC product has been successfully improved from the original ∼200V to become ≥ 3kV.

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U2 - 10.1109/ISCAS.2001.922348

DO - 10.1109/ISCAS.2001.922348

M3 - Conference article

AN - SCOPUS:0035025865

SN - 0272-9172

VL - 626

SP - IV758-IV761

JO - Materials Research Society Symposium - Proceedings

JF - Materials Research Society Symposium - Proceedings

T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications

Y2 - 24 April 2000 through 27 April 2000

ER -

Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes

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