Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process

Ming-Dou Ker*, Wen Yi Chen, Kuo Chun Hsu

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.

Original languageEnglish
Pages (from-to)2187-2193
Number of pages7
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume53
Issue number10
DOIs
StatePublished - 1 Oct 2006

Keywords

  • ESD protection circuit
  • Electrostatic discharge (ESD)
  • High-voltage tolerant
  • Power-rail ESD clamp circuit
  • Substrate-triggered technique

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