TY - GEN
T1 - Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability
AU - Ker, Ming-Dou
AU - Hu, Fang Ling
PY - 2007/9/28
Y1 - 2007/9/28
N2 - A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2×VDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-μm CMOS process to receive 3.3-V (2×VDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0.
AB - A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2×VDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-μm CMOS process to receive 3.3-V (2×VDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0.
UR - http://www.scopus.com/inward/record.url?scp=34648819539&partnerID=8YFLogxK
U2 - 10.1109/VDAT.2007.373205
DO - 10.1109/VDAT.2007.373205
M3 - Conference contribution
AN - SCOPUS:34648819539
SN - 1424405831
SN - 9781424405831
T3 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
BT - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007 - Proceedings of Technical Papers
T2 - 2007 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2007
Y2 - 25 April 2007 through 27 April 2007
ER -