Design on Mixed-Voltage I/O buffer with blocking NMOS and dynamic Gate-Controlled circuit for High-Voltage-Tolerant applications

Ming-Dou Ker, Shih Lun Chen, Chia Sheng Tsai

    Research output: Contribution to journalConference articlepeer-review

    1 Scopus citations

    Abstract

    A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltagetolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.

    Original languageEnglish
    Article number1464973
    Pages (from-to)1859-1862
    Number of pages4
    JournalProceedings - IEEE International Symposium on Circuits and Systems
    DOIs
    StatePublished - 2005
    EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
    Duration: 23 May 200526 May 2005

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