Design on Mixed-Voltage I/O buffer with blocking NMOS and dynamic Gate-Controlled circuit for High-Voltage-Tolerant applications

Ming-Dou Ker; Shih Lun Chen; Chia Sheng Tsai

doi:10.1109/ISCAS.2005.1464973

Design on Mixed-Voltage I/O buffer with blocking NMOS and dynamic Gate-Controlled circuit for High-Voltage-Tolerant applications

Ming-Dou Ker, Shih Lun Chen, Chia Sheng Tsai

Research output: Contribution to journal › Conference article › peer-review

1 Scopus citations

Abstract

A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltagetolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.

Original language	English
Article number	1464973
Pages (from-to)	1859-1862
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464973
State	Published - 1 Dec 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "Design on Mixed-Voltage I/O buffer with blocking NMOS and dynamic Gate-Controlled circuit for High-Voltage-Tolerant applications",

abstract = "A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltagetolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.",

author = "Ming-Dou Ker and Chen, {Shih Lun} and Tsai, {Chia Sheng}",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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AU - Chen, Shih Lun

AU - Tsai, Chia Sheng

PY - 2005/12/1

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N2 - A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltagetolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.

AB - A new mixed-voltage I/O buffer with a blocking NMOS and a dynamic gate-controlled circuit for high-voltagetolerant applications is proposed. The new proposed I/O buffer can receive the input signals with the voltage swing twice as high as the normal power supply voltage (VDD), which has been fabricated in a 0.25-μm CMOS process to receive 5-V input signals without suffering gate-oxide reliability and circuit leakage issues. The new proposed mixed-voltage I/O buffer can be easily scaled down toward 0.18-μm (or below) CMOS process to serve different mixed-voltage I/O interfaces, such as 1.8/3.3-V or 1.2/2.5-V applications.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1464973

Y2 - 23 May 2005 through 26 May 2005

ER -

Design on Mixed-Voltage I/O buffer with blocking NMOS and dynamic Gate-Controlled circuit for High-Voltage-Tolerant applications

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