Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

Kun Hsien Lin; Ming-Dou Ker

doi:10.1109/EOSESD.2004.5272601

Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

Kun Hsien Lin^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-μm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40V.

Original language	English
Title of host publication	2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04
DOIs	https://doi.org/10.1109/EOSESD.2004.5272601
State	Published - 1 Dec 2004
Event	2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04 - Grapevine, TX, United States Duration: 19 Sep 2004 → 23 Sep 2004

Publication series

Name	Electrical Overstress/Electrostatic Discharge Symposium Proceedings
ISSN (Print)	0739-5159

Conference

Conference	2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04
Country/Territory	United States
City	Grapevine, TX
Period	19/09/04 → 23/09/04

Access to Document

10.1109/EOSESD.2004.5272601

Cite this

@inproceedings{1480833abd354337931332c219e17c23,

title = "Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs",

abstract = "The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-μm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40V.",

author = "Lin, {Kun Hsien} and Ming-Dou Ker",

year = "2004",

month = dec,

day = "1",

doi = "10.1109/EOSESD.2004.5272601",

language = "English",

isbn = "1585370630",

series = "Electrical Overstress/Electrostatic Discharge Symposium Proceedings",

booktitle = "2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04",

note = "2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04 ; Conference date: 19-09-2004 Through 23-09-2004",

}

Lin, KH & Ker, M-D 2004, Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs. in 2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04., 5272601, Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04, Grapevine, TX, United States, 19/09/04. https://doi.org/10.1109/EOSESD.2004.5272601

Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs. / Lin, Kun Hsien; Ker, Ming-Dou.
2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04. 2004. 5272601 (Electrical Overstress/Electrostatic Discharge Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

AU - Lin, Kun Hsien

AU - Ker, Ming-Dou

PY - 2004/12/1

Y1 - 2004/12/1

N2 - The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-μm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40V.

AB - The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-μm 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40V.

UR - http://www.scopus.com/inward/record.url?scp=77950811633&partnerID=8YFLogxK

U2 - 10.1109/EOSESD.2004.5272601

DO - 10.1109/EOSESD.2004.5272601

M3 - Conference contribution

AN - SCOPUS:77950811633

SN - 1585370630

SN - 9781585370634

T3 - Electrical Overstress/Electrostatic Discharge Symposium Proceedings

BT - 2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04

T2 - 2004 Electrical Overstress/Electrostatic Discharge Symposium, EOS/ESD '04

Y2 - 19 September 2004 through 23 September 2004

ER -

Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this