Design on ESD protection scheme for IC with power-down-mode operation

Ming-Dou Ker*, Kun Hsien Lin

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    9 Scopus citations

    Abstract

    This paper presents a new electrostatic discharge (ESD) protection scheme for IC with power-down-mode operation. Adding a VDD ESD bus line and diodes into the proposed ESD protection scheme can block the leakage current from I/O pin to VDD power line and avoid malfunction during power-down operation. The whole-chip ESD protection design can be achieved by insertion of ESD clamp circuits between VSS power line and both the VDD power line and VDD ESD bus line. Experiment results show that the human-body model (HBM) ESD level of this new scheme can be greater than 7.5 kV in a 0.35-μm silicided CMOS process.

    Original languageEnglish
    Pages (from-to)1378-1382
    Number of pages5
    JournalIEEE Journal of Solid-State Circuits
    Volume39
    Issue number8
    DOIs
    StatePublished - 1 Aug 2004

    Keywords

    • Electrostatic discharge (ESD)
    • ESD bus
    • ESD protection scheme
    • Leakage current
    • Power-down mode

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