Design on ESD protection circuit with very low and constant input capacitance

Tung Yang Chen; Ming-Dou Ker

doi:10.1109/ISQED.2001.915233

Design on ESD protection circuit with very low and constant input capacitance

Tung Yang Chen, Ming-Dou Ker

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for high-frequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).

Original language	English
Title of host publication	Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001
Publisher	IEEE Computer Society
Pages	247-248
Number of pages	2
ISBN (Electronic)	0769510256
DOIs	https://doi.org/10.1109/ISQED.2001.915233
State	Published - 28 Mar 2001
Event	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 - San Jose, United States Duration: 26 Mar 2001 → 28 Mar 2001

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2001-January
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Conference

Conference	2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001
Country/Territory	United States
City	San Jose
Period	26/03/01 → 28/03/01

Access to Document

10.1109/ISQED.2001.915233

Cite this

Chen, T. Y., & Ker, M.-D. (2001). Design on ESD protection circuit with very low and constant input capacitance. In Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001 (pp. 247-248). Article 915233 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January). IEEE Computer Society. https://doi.org/10.1109/ISQED.2001.915233

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title = "Design on ESD protection circuit with very low and constant input capacitance",

abstract = "Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for high-frequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).",

author = "Chen, {Tung Yang} and Ming-Dou Ker",

year = "2001",

month = mar,

day = "28",

doi = "10.1109/ISQED.2001.915233",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE Computer Society",

pages = "247--248",

booktitle = "Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001",

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note = "2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001 ; Conference date: 26-03-2001 Through 28-03-2001",

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Chen, TY & Ker, M-D 2001, Design on ESD protection circuit with very low and constant input capacitance. in Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001., 915233, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2001-January, IEEE Computer Society, pp. 247-248, 2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001, San Jose, United States, 26/03/01. https://doi.org/10.1109/ISQED.2001.915233

Design on ESD protection circuit with very low and constant input capacitance. / Chen, Tung Yang; Ker, Ming-Dou.
Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001. IEEE Computer Society, 2001. p. 247-248 915233 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for high-frequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).

AB - Effective on-chip ESD design to solve the ESD protection challenge on the analog pins for high-frequency or current-mode applications is studied. The device dimension of ESD clamp devices in analog ESD protection circuit can be reduced to have a much small input capacitance for high-frequency applications, but it can still sustain a high HBM and MM ESD level. To find the optimized device dimensions and layout spacings on ESD clamp devices, a design model is developed to keep the input capacitance as constant as possible (within 1% variation).

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BT - Proceedings of the IEEE 2001 2nd International Symposium on Quality Electronic Design, ISQED 2001

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T2 - 2nd IEEE International Symposium on Quality Electronic Design, ISQED 2001

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Design on ESD protection circuit with very low and constant input capacitance

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