Design of VLSI implemented signal processing systems based on signal flow graph analyses

Kuei-Ann Wen; Jau Yien Lee; Jhing Fa Wang; Chang Soon Wu

doi:10.1109/ISCAS.1988.15320

Design of VLSI implemented signal processing systems based on signal flow graph analyses

Kuei-Ann Wen^*, Jau Yien Lee, Jhing Fa Wang, Chang Soon Wu

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

An efficient design approach based on signal flow graph (SFG) analyses is introduced. A common set of VLSI structures has been derived for homogeneous and shuffle-exchange SFGs and are shown to be applicable to a general set of signal processing algorithms. The feasibility of this SFG-oriented design approach is demonstrated by an efficient implementation of the convolutional encoder/decoder, which is a significant achievement for coding system design.

Original language	English
Title of host publication	Proceedings - IEEE International Symposium on Circuits and Systems
Publisher	Publ by IEEE
Pages	1947-1951
Number of pages	5
ISBN (Print)	9517212402
DOIs	https://doi.org/10.1109/ISCAS.1988.15320
State	Published - 1 Dec 1988

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
ISSN (Print)	0271-4310

Access to Document

10.1109/ISCAS.1988.15320

Cite this

@inproceedings{b23956ec54db47879e7b1eb71fe9ddc5,

title = "Design of VLSI implemented signal processing systems based on signal flow graph analyses",

abstract = "An efficient design approach based on signal flow graph (SFG) analyses is introduced. A common set of VLSI structures has been derived for homogeneous and shuffle-exchange SFGs and are shown to be applicable to a general set of signal processing algorithms. The feasibility of this SFG-oriented design approach is demonstrated by an efficient implementation of the convolutional encoder/decoder, which is a significant achievement for coding system design.",

author = "Kuei-Ann Wen and Lee, {Jau Yien} and Wang, {Jhing Fa} and Wu, {Chang Soon}",

year = "1988",

month = dec,

day = "1",

doi = "10.1109/ISCAS.1988.15320",

language = "English",

isbn = "9517212402",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Publ by IEEE",

pages = "1947--1951",

booktitle = "Proceedings - IEEE International Symposium on Circuits and Systems",

}

Design of VLSI implemented signal processing systems based on signal flow graph analyses. / Wen, Kuei-Ann; Lee, Jau Yien; Wang, Jhing Fa et al.
Proceedings - IEEE International Symposium on Circuits and Systems. Publ by IEEE, 1988. p. 1947-1951 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Design of VLSI implemented signal processing systems based on signal flow graph analyses

AU - Wen, Kuei-Ann

AU - Lee, Jau Yien

AU - Wang, Jhing Fa

AU - Wu, Chang Soon

PY - 1988/12/1

Y1 - 1988/12/1

N2 - An efficient design approach based on signal flow graph (SFG) analyses is introduced. A common set of VLSI structures has been derived for homogeneous and shuffle-exchange SFGs and are shown to be applicable to a general set of signal processing algorithms. The feasibility of this SFG-oriented design approach is demonstrated by an efficient implementation of the convolutional encoder/decoder, which is a significant achievement for coding system design.

AB - An efficient design approach based on signal flow graph (SFG) analyses is introduced. A common set of VLSI structures has been derived for homogeneous and shuffle-exchange SFGs and are shown to be applicable to a general set of signal processing algorithms. The feasibility of this SFG-oriented design approach is demonstrated by an efficient implementation of the convolutional encoder/decoder, which is a significant achievement for coding system design.

UR - http://www.scopus.com/inward/record.url?scp=0024121762&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.1988.15320

DO - 10.1109/ISCAS.1988.15320

M3 - Conference contribution

AN - SCOPUS:0024121762

SN - 9517212402

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

SP - 1947

EP - 1951

BT - Proceedings - IEEE International Symposium on Circuits and Systems

PB - Publ by IEEE

ER -

Design of VLSI implemented signal processing systems based on signal flow graph analyses

Abstract

Publication series

Access to Document

Other files and links

Fingerprint

Cite this