Design of subthreshold SRAMs for energy-efficient quality-scalable video applications

Jinn Shyan Wang*, Pei Yao Chang, Tai Shin Tang, Jia Wei Chen, Jiun-In  Guo

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

21 Scopus citations


The design of embedded subthreshold SRAMs for a quality-scalable H.264 video decoder IP is presented in this paper. In addition to the conventional 7T SRAM bitcell, we adopted power-gating techniques and multi-output dynamic circuits in order to achieve a low {\rm VDDmin, a small area overhead, and a higher operating speed. A 256×32 90-nm SRAM macro was designed for verifying the proposed design techniques. The H.264 IP provides energy-efficient scalable video decoding of 42.8 pJ/cycle for QCIF and 235 pJ/cycle for HD720 at 0.3 V and 0.7 V, respectively.

Original languageEnglish
Article number5967919
Pages (from-to)183-192
Number of pages10
JournalIEEE Journal on Emerging and Selected Topics in Circuits and Systems
Issue number2
StatePublished - 1 Jun 2011


  • embedded
  • H.264 decoder
  • SRAM
  • Subthreshold


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