Design of power-rail ESD clamp circuits with gate-leakage consideration in nanoscale CMOS technology

Electrostatic discharge (ESD) phenomenon is a charge flow when two objects with different voltage potentials reach contact. Such ESD events can cause serious damage to the integrated circuit (IC) products, during assembly, testing, and manufacturing. To protect the IC products with the required ESD specifications, typically such as 2 kV in human body model (HBM) [1] and 200 V in machine model (MM) [2], the whole-chip ESD protection scheme formed with the power-rail ESD clamp circuit had been often used in the modern IC products [3]. As shown in Figure 5.1, the power-rail ESD clamp circuit is a vital element for ESD protection under different ESD stress modes. The ESD stress modes include V _dd-to-V _ss (or V _ss-to-V _dd) ESD stress between the rails, as well as the positive-to-V _ss (PS) mode, negative-to-V _ss (NS) mode, positive-to-V _dd (PD) mode, and negative-to-V _dd (ND) mode, from input/output (I/O) to V _dd/V _ss. Therefore, the power-rail ESD clamp circuit must provide low-impedance discharging path under ESD events but keep in off-state with standby leakage current as low as possible under normal circuit operation conditions.