Design of power-rail ESD clamp circuit with ultra-low standby leakage current in nanoscale CMOS technology

Chang Tzu Wang*, Ming-Dou Ker

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    36 Scopus citations

    Abstract

    An ultra-low-leakage power-rail ESD clamp circuit, composed of the SCR device and new ESD detection circuit, has been proposed with consideration of gate current to reduce the standby leakage current. By controlling the gate current of the devices in the ESD detection circuit under a specified bias condition, the whole power-rail ESD clamp circuit can achieve an ultra-low standby leakage current. The new proposed circuit has been fabricated in a 1 V 65 nm CMOS process for experimental verification. The new proposed power-rail ESD clamp circuit can achieve 7 kV HBM and 325 V MM ESD levels while consuming only a standby leakage current of 96 nA at 1 V bias in room temperature and occupying an active area of only 49 μm × 21 μm.

    Original languageEnglish
    Article number4787573
    Pages (from-to)956-964
    Number of pages9
    JournalIEEE Journal of Solid-State Circuits
    Volume44
    Issue number3
    DOIs
    StatePublished - Mar 2009

    Keywords

    • Electrostatic discharge (ESD)
    • Gate leakage
    • Power-rail ESD clamp circuit
    • Silicon controlled rectifier (SCR)

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