Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

Chih Ting Yeh; Yung Chih Liang; Ming-Dou Ker

doi:10.1109/ISCAS.2011.5937835

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

Chih Ting Yeh^*, Yung Chih Liang, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

Original language	English
Title of host publication	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages	1403-1406
Number of pages	4
DOIs	https://doi.org/10.1109/ISCAS.2011.5937835
State	Published - 2 Aug 2011
Event	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil Duration: 15 May 2011 → 18 May 2011

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Country/Territory	Brazil
City	Rio de Janeiro
Period	15/05/11 → 18/05/11

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10.1109/ISCAS.2011.5937835

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Yeh, C. T., Liang, Y. C., & Ker, M-D. (2011). Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. In 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 (pp. 1403-1406). [5937835] (Proceedings - IEEE International Symposium on Circuits and Systems). https://doi.org/10.1109/ISCAS.2011.5937835

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title = "Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events",

abstract = "In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.",

author = "Yeh, {Chih Ting} and Liang, {Yung Chih} and Ming-Dou Ker",

year = "2011",

month = aug,

day = "2",

doi = "10.1109/ISCAS.2011.5937835",

language = "English",

isbn = "9781424494736",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

pages = "1403--1406",

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note = "2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 ; Conference date: 15-05-2011 Through 18-05-2011",

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Yeh, CT, Liang, YC & Ker, M-D 2011, Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. in 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011., 5937835, Proceedings - IEEE International Symposium on Circuits and Systems, pp. 1403-1406, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, Brazil, 15/05/11. https://doi.org/10.1109/ISCAS.2011.5937835

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. / Yeh, Chih Ting; Liang, Yung Chih; Ker, Ming-Dou.
2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011. 2011. p. 1403-1406 5937835 (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Yeh, Chih Ting

AU - Liang, Yung Chih

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PY - 2011/8/2

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N2 - In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

AB - In this work, a new design of the ESD-transient detection circuit with the n-channel metal-oxide-semiconductor (nMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been proposed and verified in a 65nm 1.2V CMOS process. As compared to the traditional RC-based ESD-transient detection circuit, the layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long turn-on duration under the ESD stress condition, as well as better immunity against mis-trigger or transient-induced latch-on event under the fast power-on and transient noise conditions.

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T3 - Proceedings - IEEE International Symposium on Circuits and Systems

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Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events

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