Design of power-aware multiplier with graceful quality-power trade-offs

Jieh Hwang Yen; Lan-Rong Dung; Chi Yuan Shen

doi:10.1109/ISCAS.2005.1464919

Design of power-aware multiplier with graceful quality-power trade-offs

Jieh Hwang Yen, Lan-Rong Dung, Chi Yuan Shen

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.

Original language	English
Article number	1464919
Pages (from-to)	1642-1645
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1464919
State	Published - 23 May 2005
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: 23 May 2005 → 26 May 2005

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title = "Design of power-aware multiplier with graceful quality-power trade-offs",

abstract = "A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.",

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AU - Yen, Jieh Hwang

AU - Dung, Lan-Rong

AU - Shen, Chi Yuan

PY - 2005/5/23

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N2 - A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.

AB - A novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.

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T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

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Design of power-aware multiplier with graceful quality-power trade-offs

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