Design of mixed-voltage I/O buffer by using NMOS-blocking technique

An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1 × V _DD devices can receive 2 ×V _DD, 3 × V _DD, and even 4 × V _DD input signal without the gate-oxide reliability issue is proposed. In this paper, the 2 × V _DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-μm 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3 × V _DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-μm 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4 × V _DD, 5 × V _DD, and even 6 × V _DD input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.