Design of memory sub-system with constant-rate bumping process for H.264/ AVC decoder

Chih Hung Li*, Wen-Hsiao Peng, Tihao Chiang

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


In this paper, we propose an efficient memory sub-system and a constant-rate bumping process for a H.264/AVC decoder conforming to High profileLevel 4. To efficiently utilize the throughput of external DRAM, a synchronization buffer is employed as a bridge for reformatting the read/write data exchanged between the onchip hardware and the off-chip DRAM. In addition, we optimize the issues of read/write commands and adaptively enable the auto-precharge function by monitoring the motion information of a submacroblock. Furthermore, a regulation buffer with size comparable to the decoded picture buffer is created to ensure a constant output rate of decoded pictures for any conformed prediction structures. Along with other modules, the proposed scheme is verified at system level using transaction level modeling (TLM) technique. Statistical results show that synchronization buffer of larger block size provides higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.

Original languageEnglish
Pages (from-to)209-217
Number of pages9
JournalIEEE Transactions on Consumer Electronics
Issue number1
StatePublished - 1 Feb 2007


  • Bumping process
  • DRAM controller
  • H.264/AVC
  • Transaction level modeling


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