TY - GEN
T1 - Design of memory sub-system in H.264/AVC decoder
AU - Li, Chih Hung
AU - Chang, Chang Hsuan
AU - Peng, Wen-Hsiao
AU - Hwang, Wei
AU - Chiang, Tihao
PY - 2007/8/24
Y1 - 2007/8/24
N2 - In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8×8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.
AB - In this paper, we present the memory sub-system of a H.264/AVC decoder designed for High profile and Level 4. Our design incorporates a synchronization buffer as a pre-cache buffer. We investigate the efficiency of DRAM access and power dissipation when the buffer is designed at different granularities. Statistical results show that the granularity of larger block size has higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8×8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.
UR - http://www.scopus.com/inward/record.url?scp=34548050437&partnerID=8YFLogxK
U2 - 10.1109/ICCE.2007.341382
DO - 10.1109/ICCE.2007.341382
M3 - Conference contribution
AN - SCOPUS:34548050437
SN - 142440763X
SN - 9781424407637
T3 - Digest of Technical Papers - IEEE International Conference on Consumer Electronics
BT - Digest of Technical Papers - 2007 International Conference on Consumer Electronics, ICCE 2007
T2 - 2007 Digest of Technical Papers International Conference on Consumer Electronics
Y2 - 10 January 2007 through 14 January 2007
ER -