Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

Po Yen Chiu; Ming-Dou Ker

doi:10.1109/ICICDT.2011.5783185

Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

Po Yen Chiu^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

10 Scopus citations

Abstract

A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

Original language	English
Title of host publication	2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
DOIs	https://doi.org/10.1109/ICICDT.2011.5783185
State	Published - 24 Jun 2011
Event	2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 - Kaohsiung, Taiwan Duration: 2 May 2011 → 4 May 2011

Publication series

Name	2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

Conference

Conference	2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011
Country/Territory	Taiwan
City	Kaohsiung
Period	2/05/11 → 4/05/11

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10.1109/ICICDT.2011.5783185

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Chiu, P. Y., & Ker, M-D. (2011). Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process. In 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 [5783185] (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011). https://doi.org/10.1109/ICICDT.2011.5783185

@inproceedings{841e98c0903e44f6a454326941f94171,

title = "Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process",

abstract = "A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.",

author = "Chiu, {Po Yen} and Ming-Dou Ker",

year = "2011",

month = jun,

day = "24",

doi = "10.1109/ICICDT.2011.5783185",

language = "English",

isbn = "9781424490202",

series = "2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011",

booktitle = "2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011",

note = "2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011 ; Conference date: 02-05-2011 Through 04-05-2011",

}

Chiu, PY & Ker, M-D 2011, Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process. in 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011., 5783185, 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011, 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011, Kaohsiung, Taiwan, 2/05/11. https://doi.org/10.1109/ICICDT.2011.5783185

Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process. / Chiu, Po Yen; Ker, Ming-Dou.
2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011. 2011. 5783185 (2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ker, Ming-Dou

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N2 - A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

AB - A power-rail electrostatic discharge (ESD) clamp circuit designed with low-leakage consideration has been proposed and verified in a 65-nm low-voltage CMOS process. By using the metal-oxide-metal (MOM) capacitor in the ESD-detection circuit, the power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has very low stand-by leakage current, as compared to the traditional design. The experimental results in the silicon chip showed that the standby leakage current is only 358 nA at room temperature (25 °C) under the power-supply voltage of 1 V, whereas the traditional design realized with the NMOS capacitor is as high as 828 μA under the same bias condition.

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SN - 9781424490202

T3 - 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

BT - 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

T2 - 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011

Y2 - 2 May 2011 through 4 May 2011

ER -

Design of low-leakage power-rail ESD clamp circuit with MOM capacitor and STSCR in a 65-nm CMOS process

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