Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

Ming-Dou Ker; Hsin Chin Jiang; Chyh Yih Chang

doi:10.1109/ASIC.2000.880752

Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

Ming-Dou Ker^*, Hsin Chin Jiang, Chyh Yih Chang

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

11 Scopus citations

Abstract

A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.

Original language	English
Article number	880752
Pages (from-to)	293-296
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.2000.880752
State	Published - 13 Sep 2000
Event	Proceedings of the 13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA Duration: 13 Sep 2000 → 16 Sep 2000

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title = "Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits",

abstract = "A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.",

author = "Ming-Dou Ker and Jiang, {Hsin Chin} and Chang, {Chyh Yih}",

year = "2000",

month = sep,

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doi = "10.1109/ASIC.2000.880752",

language = "English",

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note = "null ; Conference date: 13-09-2000 Through 16-09-2000",

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T1 - Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

AU - Ker, Ming-Dou

AU - Jiang, Hsin Chin

AU - Chang, Chyh Yih

PY - 2000/9/13

Y1 - 2000/9/13

N2 - A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.

AB - A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.

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U2 - 10.1109/ASIC.2000.880752

DO - 10.1109/ASIC.2000.880752

M3 - Conference article

AN - SCOPUS:0033696592

SN - 1063-0988

SP - 293

EP - 296

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

M1 - 880752

Y2 - 13 September 2000 through 16 September 2000

ER -

Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits

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