Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

Ming-Dou Ker; Chang Tzu Wang; Tien Hao Tang; Kuan Cheng Su

doi:10.1109/RELPHY.2007.369967

Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

Ming-Dou Ker^*, Chang Tzu Wang, Tien Hao Tang, Kuan Cheng Su

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1×VDD devices for 3×VDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-μm CMOS process with only 1.2-V devices.

Original language	English
Title of host publication	2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual
Pages	594-595
Number of pages	2
DOIs	https://doi.org/10.1109/RELPHY.2007.369967
State	Published - 25 Sep 2007
Event	45th Annual IEEE International Reliability Physics Symposium 2007, IRPS - Phoenix, AZ, United States Duration: 15 Apr 2007 → 19 Apr 2007

Publication series

Name	Annual Proceedings - Reliability Physics (Symposium)
ISSN (Print)	0099-9512

Conference

Conference	45th Annual IEEE International Reliability Physics Symposium 2007, IRPS
Country/Territory	United States
City	Phoenix, AZ
Period	15/04/07 → 19/04/07

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10.1109/RELPHY.2007.369967

Cite this

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title = "Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes",

abstract = "A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1×VDD devices for 3×VDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-μm CMOS process with only 1.2-V devices.",

author = "Ming-Dou Ker and Wang, {Chang Tzu} and Tang, {Tien Hao} and Su, {Kuan Cheng}",

year = "2007",

month = sep,

day = "25",

doi = "10.1109/RELPHY.2007.369967",

language = "English",

isbn = "1424409195",

series = "Annual Proceedings - Reliability Physics (Symposium)",

pages = "594--595",

booktitle = "2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual",

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}

Ker, M-D, Wang, CT, Tang, TH & Su, KC 2007, Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes. in 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual., 4227708, Annual Proceedings - Reliability Physics (Symposium), pp. 594-595, 45th Annual IEEE International Reliability Physics Symposium 2007, IRPS, Phoenix, AZ, United States, 15/04/07. https://doi.org/10.1109/RELPHY.2007.369967

Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes. / Ker, Ming-Dou; Wang, Chang Tzu; Tang, Tien Hao et al.
2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual. 2007. p. 594-595 4227708 (Annual Proceedings - Reliability Physics (Symposium)).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ker, Ming-Dou

AU - Wang, Chang Tzu

AU - Tang, Tien Hao

AU - Su, Kuan Cheng

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AB - A new high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit with a special ESD detection circuit realized with only 1×VDD devices for 3×VDD-tolerant mixed-voltage I/O interfaces is proposed. The proposed power-rail ESD clamp circuit with excellent ESD protection effectiveness has been verified in a 0.13-μm CMOS process with only 1.2-V devices.

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DO - 10.1109/RELPHY.2007.369967

M3 - Conference contribution

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T3 - Annual Proceedings - Reliability Physics (Symposium)

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BT - 2007 IEEE International Reliability Physics Symposium Proceedings, 45th Annual

T2 - 45th Annual IEEE International Reliability Physics Symposium 2007, IRPS

Y2 - 15 April 2007 through 19 April 2007

ER -

Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes

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