Design of High-RA STT-MRAM for Future Energy-Efficient In-Memory Computing

Ming Chun Hong, Yi Hui Su, Guan Long Chen, Yu Chen Hsin, Yao Jen Chang, Kuan Ming Chen, Shan Yi Yang, I. Jung Wang, Sk Ziaur Rahaman, Hsin Han Lee, Jeng Hua Wei, Shyh Shyuan Sheu, Wei Chung Lo, Shih Chieh Chang, Tuo Hung Hou*

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

In contrast to the low-RA STT-MRAM for memory applications, high-RA (> 500 Ω-μ m2) STT-MRAM with high cell resistance (1 M Ω) is required to support energy-efficient in-memory computing beyond 10 POPS/W. Scaling the coercive magnetic field and cell dimension and increasing the MgO thickness are found critical for enlarging RA and write margin.

Original languageEnglish
Title of host publication2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350334166
DOIs
StatePublished - 2023
Event2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan
Duration: 17 Apr 202320 Apr 2023

Publication series

Name2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Country/TerritoryTaiwan
CityHsinchu
Period17/04/2320/04/23

Fingerprint

Dive into the research topics of 'Design of High-RA STT-MRAM for Future Energy-Efficient In-Memory Computing'. Together they form a unique fingerprint.

Cite this