Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity Analyses

Narasimhulu Thoti, Yiming Li*

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

9 Scopus citations

Abstract

This work reports an emerging structure of gate-all-around ferroelectric area tunneling field-effect transistor (FATFET) by considering ferroelectric and a n-epitaxial layer enveloped around the overlapped region of the source and channel to succeed with complete area of tunneling probability. To accomplish this, ferroelectric (Hf 0.5Zr 0.5O 2) is exploited and modeled to boost the FATFET performance through internal-voltage (Vint) amplification. The corresponding modeling approach to estimate the ferroelectric parameters along with Vint calculations of the metal-ferroelectric-insulator (MFIS) option through capacitance equivalent method is addressed. Using these options the proposed device outperforms effectively in delivering superior DC and RF performance among possible options of the Si 1-xGe x ferroelectric TFETs. The significance of proposed design is examined with recently reported ferroelectric TFETs. Our results show 10-time advancement on the Ion, reduced steep or average subthreshold swing (< 25 mV/dec), frequencies higher than 150 GHz, and insignificant to linearity deviations at low bias points. Furthermore, 2-order reduction in energy efficiency is succeeded with the proposed design environment.

Original languageEnglish
Article number53
JournalNanoscale Research Letters
Volume17
Issue number1
DOIs
StatePublished - 2022

Keywords

  • Ferroelectric
  • Gate-all-around
  • Internal voltage
  • Linearity
  • n-Epitaxy
  • Nanosheet
  • Si Ge
  • Switching energy

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