TY - JOUR
T1 - Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique
AU - Ker, Ming-Dou
AU - Chen, Tung Yang
AU - Wu, Chung-Yu
PY - 1997
Y1 - 1997
N2 - Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.
AB - Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.
UR - http://www.scopus.com/inward/record.url?scp=0030681807&partnerID=8YFLogxK
U2 - 10.1109/ASIC.1997.617023
DO - 10.1109/ASIC.1997.617023
M3 - Conference article
AN - SCOPUS:0030681807
SN - 1063-0988
SP - 287
EP - 290
JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
T2 - Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit
Y2 - 7 September 1997 through 10 September 1997
ER -