Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu

doi:10.1109/ASIC.1997.617023

Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Ming-Dou Ker^*, Tung Yang Chen, Chung-Yu Wu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Conference article › peer-review

15 Scopus citations

Abstract

Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.

Original language	English
Pages (from-to)	287-290
Number of pages	4
Journal	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.1997.617023
State	Published - 1 Jan 1997
Event	Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA Duration: 7 Sep 1997 → 10 Sep 1997

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abstract = "Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.",

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AU - Ker, Ming-Dou

AU - Chen, Tung Yang

AU - Wu, Chung-Yu

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Y1 - 1997/1/1

N2 - Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.

AB - Four new device structures for power-rail ESD clamp circuits by using the substrate-triggering technique are investigated in submicron CMOS technology to improve ESD level of the protection device within a smaller silicon area. Experimental results in a 0.6-μm CMOS process have verified that the ESD clamp circuit with the double-BJT structure can provide 200% higher ESD robustness in per unit layout area as comparing to the previous design with the NMOS device.

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M3 - Conference article

AN - SCOPUS:0030681807

SN - 1063-0988

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JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Y2 - 7 September 1997 through 10 September 1997

ER -

Design of cost-efficient ESD clamp circuits for the power rails of CMOS ASIC's with substrate-triggering technique

Abstract

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