Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology

Chun Yu Lin*, Li Wei Chu, Shiang Yu Tsai, Ming-Dou Ker

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    2 Scopus citations


    Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.

    Original languageEnglish
    Article number6155079
    Pages (from-to)554-561
    Number of pages8
    JournalIEEE Transactions on Device and Materials Reliability
    Issue number3
    StatePublished - 14 Sep 2012


    • CMOS
    • electrostatic discharge (ESD) protection
    • radio frequency (RF)
    • V-band


    Dive into the research topics of 'Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology'. Together they form a unique fingerprint.

    Cite this