The dependence-graph (DG) approach is extended and applied to the systematic design of a systolic array system. Two DGs that represent two different but data-dependent process algorithms are first linked together. Tag bits are added onto index nodes in this linked DG and used to indicate the different functions to be executed on single processor element. By applying the conventional time-scheduling and node-assignment procedures to this tagged DG, the interfacing communication problem of a systolic array system can be solved and the optimal latency can be easily obtained. Using this method, an optimal linear-state solver has been designed.