Abstract
A reconfigurable message-passing network is proposed to facilitate message transportation in decoding multimode quasi-cyclic low-density parity-check (QC-LDPC) codes. By exploiting the shift-routing network (SRN) features, the decoding messages are routed in parallel to fully support those specific 19 and 3 submatrix sizes defined in IEEE 802.16e and IEEE 802.11n applications with less hardware complexity. A 6.22-mm2 QC-LDPC decoder with SRN is implemented in a 90-nm 1-Poly 9-Metal (1P9M) CMOS process. Postlayout simulation results show that the operation frequency can achieve 300 MHz, which is sufficient to process the 212-Mb/s 2304-bit and 178-Mb/s 1944-bit codeword streams for IEEE 802.16e and IEEE 802.11n systems, respectively.
Original language | English |
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Pages (from-to) | 734-738 |
Number of pages | 5 |
Journal | IEEE Transactions on Circuits and Systems I: Regular Papers |
Volume | 56 |
Issue number | 9 |
DOIs | |
State | Published - 2009 |
Keywords
- Architecture
- IEEE 802.11n
- IEEE 802.16e
- Message passing
- Network
- Quasi-cyclic low-density parity check (QC-LDPC)
- WiMax