Design of a 3rd-Order 12-bit Incremental ADC for Power Monitoring Applications

Chia Min Lai*, Chung Chih Hung

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

The incremental ADC is an analog-to-digital converter with high-resolution, high-linearity, and power-efficient properties. It is especially suitable for multi-channel input sensor applications. In this paper, we propose a 3rd- order incremental ADC (IADC) designed for power monitoring applications. The proposed IADC was implemented with switched-capacitor integrators and cascade integrator feed-forward (CIFF) architecture. The design procedures, including high-level macro-model and SPICE-level simulations, are also presented. The proposed incremental ADC has a maximum of 14.7 ENOB while consuming 62.27 μ W.

Original languageEnglish
Title of host publicationAPCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages740-743
Number of pages4
ISBN (Electronic)9798350378771
DOIs
StatePublished - 2024
Event20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024 - Taipei, Taiwan
Duration: 7 Nov 20249 Nov 2024

Publication series

NameAPCCAS and PrimeAsia 2024 - 2024 IEEE 20th Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, Proceeding

Conference

Conference20th IEEE Asia Pacific Conference on Circuits and Systems and IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics Electronics, APCCAS and PrimeAsia 2024
Country/TerritoryTaiwan
CityTaipei
Period7/11/249/11/24

Keywords

  • Delta-Sigma ADC
  • Incremental ADC

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