Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit against False Trigger during Fast Power-ON Events

Han Sheng Huang, Ming Dou Ker

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    Abstract

    A new 2xVDD-tolerant power-rail ESD clamp circuit with voltage-level detection realized by 1xVDD devices is proposed against false trigger issue under fast power-on condition. All the 1xVDD devices in the proposed 2xVDD-tolerant ESD circuit are safely operated without gate oxide reliability issue. The proposed ESD clamp circuit has been implemented and verified in a 0.18-μm CMOS technology with 1.8-V devices. The experimental results have confirmed that the proposed ESD clamp circuit sustains a good HBM ESD level of 5.25kV and high immunity against false trigger issue under fast power-on condition. Moreover, polysilicon diodes are also verified to further reduce the stand-by leakage current of the proposed 2xVDD-tolerant power-rail ESD clamp circuit.

    Original languageEnglish
    Title of host publication2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    ISBN (Electronic)9781665419154
    DOIs
    StatePublished - 19 Apr 2021
    Event2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Hsinchu, Taiwan
    Duration: 19 Apr 202122 Apr 2021

    Publication series

    Name2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021 - Proceedings

    Conference

    Conference2021 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2021
    Country/TerritoryTaiwan
    CityHsinchu
    Period19/04/2122/04/21

    Keywords

    • 2xVDD-tolerant
    • ESD
    • false trigger issue
    • polysilicon diodes
    • voltage detection

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