TY - GEN
T1 - Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation
AU - Tsai, Hui Wen
AU - Ker, Ming-Dou
PY - 2007/12/1
Y1 - 2007/12/1
N2 - A new 2×VDD-tolerant I/O buffer circuit, realized with only 1×VDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2×VDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2×VDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application.
AB - A new 2×VDD-tolerant I/O buffer circuit, realized with only 1×VDD devices in nanoscale CMOS technology, to prevent transistors against gate-oxide reliability and hot-carrier degradation is proposed. The new proposed 2×VDD-tolerant I/O buffer has been implemented in a 130-nm CMOS process to serve a 2.5-V/1.2-V mixed-voltage interface without using the additional thick gate-oxide (2.5-V) devices. This 2×VDD-tolerant I/O buffer has been successfully confirmed by the experimental results with a signal speed of up to 133 MHz for PCI-X application.
UR - http://www.scopus.com/inward/record.url?scp=50649096363&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2007.4511221
DO - 10.1109/ICECS.2007.4511221
M3 - Conference contribution
AN - SCOPUS:50649096363
SN - 1424413788
SN - 9781424413782
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 1240
EP - 1243
BT - ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
T2 - 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
Y2 - 11 December 2007 through 14 December 2007
ER -