A low-leakage 2×VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit composed of the silicon-controlled rectifier (SCR) device and new ESD detection circuit, realized with only thin-oxide 1× VDD devices, has been proposed with consideration of gate leakage current. By reducing the voltage across the gate oxides of the devices in the ESD detection circuit, the whole power-rail ESD clamp circuit can achieve an ultralow standby leakage current. The new proposed circuit has successfully been verified in a 1-V 65-nm CMOS process, which can achieve 6.5-kV human-body-model and 350-V machine-model ESD levels under ESD stresses, but only consumes a standby leakage current of 0.15 μA at room temperature under normal circuit operating conditions with 1.8-V bias.
|Number of pages||6|
|Journal||IEEE Transactions on Electron Devices|
|State||Published - 1 Jun 2010|
- Electrostatic discharge (ESD)
- Gate leakage
- Mixed-voltage input/output (I/O)
- Silicon-controlled rectifier (SCR)