Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology

Po Yen Chiu; Ming-Dou Ker

doi:10.1109/SOCC.2013.6749656

Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The novel 2×V_DD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×V _DD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×V_DD tolerant capability. Thus, the new 2×V_DD logic gates can be operated under 2×V_DD voltage environment without suffering the gate-oxide reliability issue.

Original language	English
Title of host publication	Proceedings - IEEE 26th International SOC Conference, SOCC 2013
Publisher	IEEE Computer Society
Pages	33-36
Number of pages	4
ISBN (Print)	9781479911660
DOIs	https://doi.org/10.1109/SOCC.2013.6749656
State	Published - 1 Jan 2013
Event	26th IEEE International System-on-Chip Conference, SOCC 2013 - Erlangen, Germany Duration: 4 Sep 2013 → 6 Sep 2013

Publication series

Name	International System on Chip Conference
ISSN (Print)	2164-1676
ISSN (Electronic)	2164-1706

Conference

Conference	26th IEEE International System-on-Chip Conference, SOCC 2013
Country/Territory	Germany
City	Erlangen
Period	4/09/13 → 6/09/13

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10.1109/SOCC.2013.6749656

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title = "Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology",

abstract = "The novel 2×VDD NOT, NAND, and NOR logic gates have been designed and implemented in a nanoscale CMOS process with only 1×V DD devices. With the proposed dynamic source bias technique, the logic gates can be designed to have 2×VDD tolerant capability. Thus, the new 2×VDD logic gates can be operated under 2×VDD voltage environment without suffering the gate-oxide reliability issue.",

author = "Chiu, {Po Yen} and Ming-Dou Ker",

year = "2013",

month = jan,

day = "1",

doi = "10.1109/SOCC.2013.6749656",

language = "English",

isbn = "9781479911660",

series = "International System on Chip Conference",

publisher = "IEEE Computer Society",

pages = "33--36",

booktitle = "Proceedings - IEEE 26th International SOC Conference, SOCC 2013",

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note = "26th IEEE International System-on-Chip Conference, SOCC 2013 ; Conference date: 04-09-2013 Through 06-09-2013",

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Chiu, PY & Ker, M-D 2013, Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology. in Proceedings - IEEE 26th International SOC Conference, SOCC 2013., 6749656, International System on Chip Conference, IEEE Computer Society, pp. 33-36, 26th IEEE International System-on-Chip Conference, SOCC 2013, Erlangen, Germany, 4/09/13. https://doi.org/10.1109/SOCC.2013.6749656

Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology. / Chiu, Po Yen; Ker, Ming-Dou.
Proceedings - IEEE 26th International SOC Conference, SOCC 2013. IEEE Computer Society, 2013. p. 33-36 6749656 (International System on Chip Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Design of 2×VDD logic gates with only 1×V DD devices in nanoscale CMOS technology

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