Design and optimization methodology for 3D RRAM arrays

Yexin Deng; Hong Yu Chen; Bin Gao; Shimeng Yu; Shih Chieh Wu; Liang Zhao; Bing Chen; Zizhen Jiang; Xiaoyan Liu; Tuo-Hung Hou; Yoshio Nishi; Jinfeng Kang; H. S.Philip Wong

doi:10.1109/IEDM.2013.6724693

Design and optimization methodology for 3D RRAM arrays

Yexin Deng, Hong Yu Chen, Bin Gao, Shimeng Yu, Shih Chieh Wu, Liang Zhao, Bing Chen, Zizhen Jiang, Xiaoyan Liu, Tuo-Hung Hou, Yoshio Nishi, Jinfeng Kang, H. S.Philip Wong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

31 Scopus citations

Abstract

3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

Original language	English
Title of host publication	2013 IEEE International Electron Devices Meeting, IEDM 2013
Pages	25.7.1-25.7.4
Number of pages	4
DOIs	https://doi.org/10.1109/IEDM.2013.6724693
State	Published - 9 Dec 2013
Event	2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States Duration: 9 Dec 2013 → 11 Dec 2013

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Conference

Conference	2013 IEEE International Electron Devices Meeting, IEDM 2013
Country/Territory	United States
City	Washington, DC
Period	9/12/13 → 11/12/13

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/IEDM.2013.6724693

Cite this

Deng, Y., Chen, H. Y., Gao, B., Yu, S., Wu, S. C., Zhao, L., Chen, B., Jiang, Z., Liu, X., Hou, T-H., Nishi, Y., Kang, J., & Wong, H. S. P. (2013). Design and optimization methodology for 3D RRAM arrays. In 2013 IEEE International Electron Devices Meeting, IEDM 2013 (pp. 25.7.1-25.7.4). Article 6724693 (Technical Digest - International Electron Devices Meeting, IEDM). https://doi.org/10.1109/IEDM.2013.6724693

@inproceedings{05febc82f03d478d95f650a04efeddbb,

title = "Design and optimization methodology for 3D RRAM arrays",

abstract = "3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.",

author = "Yexin Deng and Chen, {Hong Yu} and Bin Gao and Shimeng Yu and Wu, {Shih Chieh} and Liang Zhao and Bing Chen and Zizhen Jiang and Xiaoyan Liu and Tuo-Hung Hou and Yoshio Nishi and Jinfeng Kang and Wong, {H. S.Philip}",

year = "2013",

month = dec,

day = "9",

doi = "10.1109/IEDM.2013.6724693",

language = "English",

isbn = "9781479923076",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

pages = "25.7.1--25.7.4",

booktitle = "2013 IEEE International Electron Devices Meeting, IEDM 2013",

note = "2013 IEEE International Electron Devices Meeting, IEDM 2013 ; Conference date: 09-12-2013 Through 11-12-2013",

}

Deng, Y, Chen, HY, Gao, B, Yu, S, Wu, SC, Zhao, L, Chen, B, Jiang, Z, Liu, X, Hou, T-H, Nishi, Y, Kang, J & Wong, HSP 2013, Design and optimization methodology for 3D RRAM arrays. in 2013 IEEE International Electron Devices Meeting, IEDM 2013., 6724693, Technical Digest - International Electron Devices Meeting, IEDM, pp. 25.7.1-25.7.4, 2013 IEEE International Electron Devices Meeting, IEDM 2013, Washington, DC, United States, 9/12/13. https://doi.org/10.1109/IEDM.2013.6724693

TY - GEN

T1 - Design and optimization methodology for 3D RRAM arrays

AU - Deng, Yexin

AU - Chen, Hong Yu

AU - Gao, Bin

AU - Yu, Shimeng

AU - Wu, Shih Chieh

AU - Zhao, Liang

AU - Chen, Bing

AU - Jiang, Zizhen

AU - Liu, Xiaoyan

AU - Hou, Tuo-Hung

AU - Nishi, Yoshio

AU - Kang, Jinfeng

AU - Wong, H. S.Philip

PY - 2013/12/9

Y1 - 2013/12/9

N2 - 3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

AB - 3D RRAM arrays are studied at the device- and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.

UR - http://www.scopus.com/inward/record.url?scp=84894346054&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2013.6724693

DO - 10.1109/IEDM.2013.6724693

M3 - Conference contribution

AN - SCOPUS:84894346054

SN - 9781479923076

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 25.7.1-25.7.4

BT - 2013 IEEE International Electron Devices Meeting, IEDM 2013

T2 - 2013 IEEE International Electron Devices Meeting, IEDM 2013

Y2 - 9 December 2013 through 11 December 2013

ER -

Design and optimization methodology for 3D RRAM arrays

Abstract

Publication series

Conference

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this