Design and implementation of synchronization detection for IEEE 802.15.3c

Ya Shiue Huang; Wei Chang Liu; Shyh-Jye Jou

doi:10.1109/VDAT.2011.5783583

Design and implementation of synchronization detection for IEEE 802.15.3c

Ya Shiue Huang^*, Wei Chang Liu, Shyh-Jye Jou

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).

Original language	English
Title of host publication	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Pages	83-86
Number of pages	4
DOIs	https://doi.org/10.1109/VDAT.2011.5783583
State	Published - 2011
Event	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan Duration: 25 Apr 2011 → 28 Apr 2011

Publication series

Name	Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

Conference

Conference	2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
Country/Territory	Taiwan
City	Hsinchu
Period	25/04/11 → 28/04/11

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10.1109/VDAT.2011.5783583

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Huang, Y. S., Liu, W. C., & Jou, S.-J. (2011). Design and implementation of synchronization detection for IEEE 802.15.3c. In Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 (pp. 83-86). Article 5783583 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011). https://doi.org/10.1109/VDAT.2011.5783583

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title = "Design and implementation of synchronization detection for IEEE 802.15.3c",

abstract = "In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).",

author = "Huang, {Ya Shiue} and Liu, {Wei Chang} and Shyh-Jye Jou",

year = "2011",

doi = "10.1109/VDAT.2011.5783583",

language = "English",

isbn = "9781424484997",

series = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

pages = "83--86",

booktitle = "Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011",

note = "2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 ; Conference date: 25-04-2011 Through 28-04-2011",

}

Huang, YS, Liu, WC & Jou, S-J 2011, Design and implementation of synchronization detection for IEEE 802.15.3c. in Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011., 5783583, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, pp. 83-86, 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011, Hsinchu, Taiwan, 25/04/11. https://doi.org/10.1109/VDAT.2011.5783583

Design and implementation of synchronization detection for IEEE 802.15.3c. / Huang, Ya Shiue; Liu, Wei Chang; Jou, Shyh-Jye.
Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011. 2011. p. 83-86 5783583 (Proceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Design and implementation of synchronization detection for IEEE 802.15.3c

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