Design and implementation of synchronization detection for IEEE 802.15.3c

Ya Shiue Huang*, Wei Chang Liu, Shyh-Jye Jou

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    9 Scopus citations

    Abstract

    In this paper, a jointed preamble/boundary detection and fractional carrier frequency offset (CFO) estimation design is presented which supports dual SC/HSI modes of IEEE 802.15.3c applications. Based on correlation based algorithms which utilizes the structure of preamble, an efficiency architecture is proposed which realizes synchronization detection with a sequential detection scheme and only single hardware for dual modes and three detection operations. In order to achieve the requirement of sampling rate, the architecture is 8x parallelism and operates at 330 MHz clock rate. The total gate count is 189k in 65 nm 1P9M CMOS process with power consumption of 60.16 mW including memory elements which occupies 63.26 % and can be shared with the frequency domain equalizer (FDE).

    Original languageEnglish
    Title of host publicationProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    Pages83-86
    Number of pages4
    DOIs
    StatePublished - 28 Jun 2011
    Event2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011 - Hsinchu, Taiwan
    Duration: 25 Apr 201128 Apr 2011

    Publication series

    NameProceedings of 2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011

    Conference

    Conference2011 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2011
    Country/TerritoryTaiwan
    CityHsinchu
    Period25/04/1128/04/11

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