Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Shao Cheng Wang*, Geng Cing Lin, Yi Wei Lin, Ming Chien Tsai, Yi Wei Chiu, Shyh-Jye Jou, Ching Te Chuang, Nan Chun Lien, Wei Chiang Shih, Kuen Di Lee, Jyun Kai Chu

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    3 Scopus citations

    Abstract

    We present an all-digital monitor structure to measure the Write Margin (WM) with dynamic Word-Line (WL) pulse for standard CMOS 6T SRAM. Ring oscillator and frequency divider based structures are used to generate wide range WL pulses (150ps ∼ 32ns) with resolution of 50ps. The bit-line voltage is then successively stepped down for dynamic Write Margin characterization under given word-line pulse width. An improved Skitter based structure is employed to measure the WL pulse width with resolution of 10 ∼ 20ps. Implementation of a 256Kb test chip in UMC 55nm Standard Performance (SP) CMOS technology is described.

    Original languageEnglish
    Title of host publication2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
    Pages116-119
    Number of pages4
    DOIs
    StatePublished - 1 Dec 2012
    Event2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012 - Kaohsiung, Taiwan
    Duration: 2 Dec 20125 Dec 2012

    Publication series

    NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

    Conference

    Conference2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
    Country/TerritoryTaiwan
    CityKaohsiung
    Period2/12/125/12/12

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