Design and exploration of vertically stacked complementary tunneling field-effect transistors

The purpose of this letter is to study the design and explore vertically stacked complementary tunneling field-effect transistors (CTFETs) using CFET technology for emerging technology nodes. As a prior work, the CTFET’s device-level simulations are implemented and deliberated in strict compliance with the experimental settings. This work comprises the study of physical and DC analyses by scaling the p- to n-CTFET separation (D _pn ), being a significant factor in CFET/CTFET design for its process difficulty. By utilizing the 50% benefit in footprint, the work is further extended to CTFET static random access memory implementation and characterization with hold/read noise margin analysis.