Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Bing Yue Tsui*, Te Kai Tsai, Chia Lung Hung, Yu Xin Wen

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.

Original languageEnglish
Title of host publication2022 International Electron Devices Meeting, IEDM 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages931-934
Number of pages4
ISBN (Electronic)9781665489591
DOIs
StatePublished - 2022
Event2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States
Duration: 3 Dec 20227 Dec 2022

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2022-December
ISSN (Print)0163-1918

Conference

Conference2022 International Electron Devices Meeting, IEDM 2022
Country/TerritoryUnited States
CitySan Francisco
Period3/12/227/12/22

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