Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Bing Yue Tsui; Te Kai Tsai; Chia Lung Hung; Yu Xin Wen

doi:10.1109/IEDM45625.2022.10019434

Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

Bing Yue Tsui^*, Te Kai Tsai, Chia Lung Hung, Yu Xin Wen

^*Corresponding author for this work

Institute of Electronics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

7 Scopus citations

Abstract

Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.

Original language	English
Title of host publication	2022 International Electron Devices Meeting, IEDM 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	931-934
Number of pages	4
ISBN (Electronic)	9781665489591
DOIs	https://doi.org/10.1109/IEDM45625.2022.10019434
State	Published - 2022
Event	2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States Duration: 3 Dec 2022 → 7 Dec 2022

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
Volume	2022-December
ISSN (Print)	0163-1918

Conference

Conference	2022 International Electron Devices Meeting, IEDM 2022
Country/Territory	United States
City	San Francisco
Period	3/12/22 → 7/12/22

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10.1109/IEDM45625.2022.10019434

Cite this

Tsui, B. Y., Tsai, T. K., Hung, C. L., & Wen, Y. X. (2022). Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C. In 2022 International Electron Devices Meeting, IEDM 2022 (pp. 931-934). (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2022-December). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM45625.2022.10019434

Tsui, Bing Yue ; Tsai, Te Kai ; Hung, Chia Lung et al. / Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C. 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 931-934 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{f68835dbe7a949dcb08fd6cce9f5f36c,

title = "Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C",

abstract = "Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.",

author = "Tsui, {Bing Yue} and Tsai, {Te Kai} and Hung, {Chia Lung} and Wen, {Yu Xin}",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 International Electron Devices Meeting, IEDM 2022 ; Conference date: 03-12-2022 Through 07-12-2022",

year = "2022",

doi = "10.1109/IEDM45625.2022.10019434",

language = "English",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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address = "美國",

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Tsui, BY, Tsai, TK, Hung, CL & Wen, YX 2022, Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C. in 2022 International Electron Devices Meeting, IEDM 2022. Technical Digest - International Electron Devices Meeting, IEDM, vol. 2022-December, Institute of Electrical and Electronics Engineers Inc., pp. 931-934, 2022 International Electron Devices Meeting, IEDM 2022, San Francisco, United States, 3/12/22. https://doi.org/10.1109/IEDM45625.2022.10019434

Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C. / Tsui, Bing Yue; Tsai, Te Kai; Hung, Chia Lung et al.
2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 931-934 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2022-December).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

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AU - Tsai, Te Kai

AU - Hung, Chia Lung

AU - Wen, Yu Xin

PY - 2022

Y1 - 2022

N2 - Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.

AB - Monolithic integration of 4H-SiC CMOS and VDMOSFET is an attractive technology to realize smart power integrated circuits. The isolation between the PMOSFET of CMOS and the high voltage drain of the VDMOSFET is a critical demand. In this work, the design criteria of the buried junction isolation structure, named P-iso structure, for 600-V-class MOSFET are investigated for the first time. With proper design, the P-iso structure achieves breakdown voltage higher than 800 V and functions at 300 °C with substrate bias at 600 V. It is also predicted that the P-iso technology can be used for higher voltage applications.

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Tsui BY, Tsai TK, Hung CL, Wen YX. Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C. In 2022 International Electron Devices Meeting, IEDM 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 931-934. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM45625.2022.10019434

Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C

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