Design and Characterization of n/p-well CMOS SPAD with Low Dark Count Rate and High Photon Detection Efficiency

Jau Yang Wu; Chun Hsien Liu

doi:10.1109/TED.2022.3231575

Design and Characterization of n/p-well CMOS SPAD with Low Dark Count Rate and High Photon Detection Efficiency

Jau Yang Wu^*, Chun Hsien Liu

^*Corresponding author for this work

Institute of Electronics

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

We have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18- μm high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).

Original language	English
Pages (from-to)	582-587
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	70
Issue number	2
DOIs	https://doi.org/10.1109/TED.2022.3231575
State	Published - 1 Feb 2023

Keywords

CMOS sensor
light detection and ranging (LiDAR)
photodetector
single-photon avalanche diode (SPAD)

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10.1109/TED.2022.3231575

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title = "Design and Characterization of n/p-well CMOS SPAD with Low Dark Count Rate and High Photon Detection Efficiency",

abstract = "We have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18- μm high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).",

keywords = "CMOS sensor, light detection and ranging (LiDAR), photodetector, single-photon avalanche diode (SPAD)",

author = "Wu, {Jau Yang} and Liu, {Chun Hsien}",

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AB - We have proposed a structure design of single-photon avalanche diode fabricated in the Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) 0.18- μm high-voltage (HV) CMOS technology, which improves the limited operating excess voltage for an n-on-p design without any other customized well layer. With the introduction of a deep p-well isolation (ISO) layer, the excess bias is significantly elevated, so that the device exhibits high photon detection probability (PDP) with relatively low dark count rate. The n-on-p-type device is favorable for 3-D-stacked backside illuminated structure and can attain high PDP at longer wavelength. With the improved jitter and after-pulsing probability, our designed device can be suitable for the application of light detection and ranging (LiDAR).

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Design and Characterization of n/p-well CMOS SPAD with Low Dark Count Rate and High Photon Detection Efficiency

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