Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications

Ming-Dou Ker; Tung Yang Chen; Chung-Yu Wu; Hun Hsien Chang

doi:10.1109/ISCAS.2000.857363

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications

Ming-Dou Ker^*, Tung Yang Chen, Chung-Yu Wu, Hun Hsien Chang

^*Corresponding author for this work

Research output: Contribution to journal › Conference article › peer-review

3 Scopus citations

Abstract

An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approximately 1.0 pF (including the bond pad capacitance) for high-frequency applications.

Original language	English
Article number	857363
Pages (from-to)	61-64
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	5
DOIs	https://doi.org/10.1109/ISCAS.2000.857363
State	Published - 28 May 2000
Event	Proceedings of the IEEE 2000 International Symposium on Circuits and Systems - Geneva, Switz Duration: 28 May 2000 → 31 May 2000

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title = "Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications",

abstract = "An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approximately 1.0 pF (including the bond pad capacitance) for high-frequency applications.",

author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Wu and Chang, {Hun Hsien}",

year = "2000",

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doi = "10.1109/ISCAS.2000.857363",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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note = "null ; Conference date: 28-05-2000 Through 31-05-2000",

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Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications. / Ker, Ming-Dou; Chen, Tung Yang; Wu, Chung-Yu et al.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 5, 857363, 28.05.2000, p. 61-64.

Research output: Contribution to journal › Conference article › peer-review

TY - JOUR

T1 - Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications

AU - Ker, Ming-Dou

AU - Chen, Tung Yang

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

PY - 2000/5/28

Y1 - 2000/5/28

N2 - An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approximately 1.0 pF (including the bond pad capacitance) for high-frequency applications.

AB - An on-chip ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-precision applications. A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices has been developed to keep the total input capacitance almost constant (within 1% variation), even if the analog signal has an input dynamic range of 1 V. The device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only approximately 1.0 pF (including the bond pad capacitance) for high-frequency applications.

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EP - 64

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

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Y2 - 28 May 2000 through 31 May 2000

ER -

Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications

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