Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process

Ming-Dou Ker; Tai Xiang Lai

doi:10.1109/RELPHY.2006.251298

Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process

Ming-Dou Ker^*, Tai Xiang Lai

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-μm salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.

Original language	English
Title of host publication	2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual
Pages	633-634
Number of pages	2
DOIs	https://doi.org/10.1109/RELPHY.2006.251298
State	Published - 1 Dec 2006
Event	44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 - San Jose, CA, United States Duration: 26 Mar 2006 → 30 Mar 2006

Publication series

Name	IEEE International Reliability Physics Symposium Proceedings
ISSN (Print)	1541-7026

Conference

Conference	44th Annual IEEE International Reliability Physics Symposium, IRPS 2006
Country/Territory	United States
City	San Jose, CA
Period	26/03/06 → 30/03/06

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10.1109/RELPHY.2006.251298

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Ker, M-D., & Lai, T. X. (2006). Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process. In 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual (pp. 633-634). [4017239] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/RELPHY.2006.251298

@inproceedings{554d62c78f114a0180d9ed98cf0ca0d7,

title = "Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process",

abstract = "In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-μm salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.",

author = "Ming-Dou Ker and Lai, {Tai Xiang}",

year = "2006",

month = dec,

day = "1",

doi = "10.1109/RELPHY.2006.251298",

language = "English",

isbn = "0780394992",

series = "IEEE International Reliability Physics Symposium Proceedings",

pages = "633--634",

booktitle = "2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual",

note = "44th Annual IEEE International Reliability Physics Symposium, IRPS 2006 ; Conference date: 26-03-2006 Through 30-03-2006",

}

Ker, M-D & Lai, TX 2006, Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process. in 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual., 4017239, IEEE International Reliability Physics Symposium Proceedings, pp. 633-634, 44th Annual IEEE International Reliability Physics Symposium, IRPS 2006, San Jose, CA, United States, 26/03/06. https://doi.org/10.1109/RELPHY.2006.251298

Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process. / Ker, Ming-Dou; Lai, Tai Xiang.
2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual. 2006. p. 633-634 4017239 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process

AU - Ker, Ming-Dou

AU - Lai, Tai Xiang

PY - 2006/12/1

Y1 - 2006/12/1

N2 - In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-μm salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.

AB - In this paper, the long-pulse transmission line pulsing (LP-TLP) system is proposed to simulate the influence of Cable Discharge Event (CDE) on integrated circuits. The layout dependence on CDE robustness of gate-grounded NMOS (GGNMOS) and gate-VDD PMOS (GDPMOS) devices has been experimentally investigated in detail. All CMOS devices with different device dimensions, layout spacings, and clearances have been drawn and fabricated in a 0.25-μm salicided CMOS process to find optimum layout rules for CDE protection. From the measured results, the CDE robustness of CMOS devices is much worse than their HBM ESD robustness.

UR - http://www.scopus.com/inward/record.url?scp=34250745199&partnerID=8YFLogxK

U2 - 10.1109/RELPHY.2006.251298

DO - 10.1109/RELPHY.2006.251298

M3 - Conference contribution

AN - SCOPUS:34250745199

SN - 0780394992

SN - 0780394984

SN - 9780780394988

T3 - IEEE International Reliability Physics Symposium Proceedings

SP - 633

EP - 634

BT - 2006 IEEE International Reliability Physics Symposium Proceedings, 44th Annual

T2 - 44th Annual IEEE International Reliability Physics Symposium, IRPS 2006

Y2 - 26 March 2006 through 30 March 2006

ER -

Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in A 0.25-μM salicided CMOS process

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