Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs

Sheng Fu Hsu; Ming-Dou Ker

doi:10.1109/TED.2007.892013

Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs

Sheng Fu Hsu^*, Ming-Dou Ker

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

The dependence of device structures on latchup immunity in a 0.25-μm high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process.

Original language	English
Pages (from-to)	840-851
Number of pages	12
Journal	IEEE Transactions on Electron Devices
Volume	54
Issue number	4
DOIs	https://doi.org/10.1109/TED.2007.892013
State	Published - 1 Apr 2007

Keywords

Drain-extended MOS (DEMOS)
High-voltage (HV) CMOS process
Latchup
Silicon-controlled rectifier (SCR)
Transmission line pulsing (TLP)

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10.1109/TED.2007.892013

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title = "Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs",

abstract = "The dependence of device structures on latchup immunity in a 0.25-μm high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process.",

keywords = "Drain-extended MOS (DEMOS), High-voltage (HV) CMOS process, Latchup, Silicon-controlled rectifier (SCR), Transmission line pulsing (TLP)",

author = "Hsu, {Sheng Fu} and Ming-Dou Ker",

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AU - Hsu, Sheng Fu

AU - Ker, Ming-Dou

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N2 - The dependence of device structures on latchup immunity in a 0.25-μm high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process.

AB - The dependence of device structures on latchup immunity in a 0.25-μm high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process.

KW - Drain-extended MOS (DEMOS)

KW - High-voltage (HV) CMOS process

KW - Latchup

KW - Silicon-controlled rectifier (SCR)

KW - Transmission line pulsing (TLP)

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JF - Ieee Transactions On Electron Devices

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Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs

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