Demonstration of Lowerature Fine-Pitch Cu/SiO2Hybrid Bonding by Au Passivation

Demin Liu; Po Chih Chen; Tzu Chieh Chou; Han Wen Hu; Kuan Neng Chen

doi:10.1109/JEDS.2021.3114648

Demonstration of Lowerature Fine-Pitch Cu/SiO₂Hybrid Bonding by Au Passivation

Demin Liu, Po Chih Chen, Tzu Chieh Chou, Han Wen Hu, Kuan Neng Chen^*

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

41 Scopus citations

Abstract

Fine pitch Cu/SiO22 hybrid bonding has been successfully demonstrated at a low temperature of 120 °C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO22 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO22 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications.

Original language	English
Pages (from-to)	868-875
Number of pages	8
Journal	IEEE Journal of the Electron Devices Society
Volume	9
DOIs	https://doi.org/10.1109/JEDS.2021.3114648
State	Published - Sep 2021

Keywords

3D integration
Au passivation
Cu bonding
flip-chip bonding
wafer-level bonding

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title = "Demonstration of Lowerature Fine-Pitch Cu/SiO2Hybrid Bonding by Au Passivation",

abstract = "Fine pitch Cu/SiO22 hybrid bonding has been successfully demonstrated at a low temperature of 120 °C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO22 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO22 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications. ",

keywords = "3D integration, Au passivation, Cu bonding, flip-chip bonding, wafer-level bonding",

author = "Demin Liu and Chen, {Po Chih} and Chou, {Tzu Chieh} and Hu, {Han Wen} and Chen, {Kuan Neng}",

note = "Publisher Copyright: {\textcopyright} 2013 IEEE.",

year = "2021",

month = sep,

doi = "10.1109/JEDS.2021.3114648",

language = "English",

volume = "9",

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journal = "IEEE Journal of the Electron Devices Society",

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T1 - Demonstration of Lowerature Fine-Pitch Cu/SiO2Hybrid Bonding by Au Passivation

AU - Liu, Demin

AU - Chen, Po Chih

AU - Chou, Tzu Chieh

AU - Hu, Han Wen

AU - Chen, Kuan Neng

PY - 2021/9

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N2 - Fine pitch Cu/SiO22 hybrid bonding has been successfully demonstrated at a low temperature of 120 °C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO22 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO22 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications.

AB - Fine pitch Cu/SiO22 hybrid bonding has been successfully demonstrated at a low temperature of 120 °C, a breakthrough, using Au passivation method in this work. To explore the bonding mechanism of passivation structures for hybrid bonding in details, Cu-Cu direct bonding with Au passivation on both wafer-level and chip-level has been discussed, including analyses of AFM, SAT, TEM, electrical measurements, and reliability test. Cu/SiO22 hybrid bonding with the fine pitch structure with stable electrical performance can be achieved at low bonding temperature under an atmospheric environment. Accordingly, this Au passivation scheme for Cu/SiO22 hybrid bonding with excellent bonding quality, low thermal budget, and high reliability shows a great feasibility for the 3D IC and heterogenous integration applications.

KW - 3D integration

KW - Au passivation

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Demonstration of Lowerature Fine-Pitch Cu/SiO₂Hybrid Bonding by Au Passivation

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