TY - GEN
T1 - Demonstration of Differential Mode FeFET-Array for multi-precision storage and IMC applications
AU - Parmar, Vivek
AU - Muller, Franz
AU - Hsuen, Jing Hua
AU - Kingra, Sandeep Kaur
AU - Raffel, Yannick
AU - Lederer, Maximillian
AU - Ali, Tarek
AU - Dunkel, Stefan
AU - Seidel, Konrad
AU - Beyer, Sven
AU - Wu, Tian Li
AU - Kampfe, Thomas
AU - De, Sourav
AU - Suri, Manan
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Harnessing multibit precision in non-volatile memory (NVM) based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM-based synaptic cores suffer from the trade-off between bit density and performance. The undesired performance degradation with scaling, limited bit precision, and asymmetry associated with weight update poses a severe bottleneck in realizing a high-density synaptic core. In this work, we demonstrate: (i) implementation of novel differential mode ferroelectric field effect transistor (FeFET) (DM-FeFET) based multibit crossbar array of 12 Kbit size. (ii) bit density of 223Mb/mm2, which is ∼2x improvement compared to conventional FeFET array; (iii) 196 TOPS/W energy efficiency for VGG-8 network and (iv) superior bit error rate (BER) resilience showing ∼94% training and 88% inference accuracy with 1% BER.
AB - Harnessing multibit precision in non-volatile memory (NVM) based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM-based synaptic cores suffer from the trade-off between bit density and performance. The undesired performance degradation with scaling, limited bit precision, and asymmetry associated with weight update poses a severe bottleneck in realizing a high-density synaptic core. In this work, we demonstrate: (i) implementation of novel differential mode ferroelectric field effect transistor (FeFET) (DM-FeFET) based multibit crossbar array of 12 Kbit size. (ii) bit density of 223Mb/mm2, which is ∼2x improvement compared to conventional FeFET array; (iii) 196 TOPS/W energy efficiency for VGG-8 network and (iv) superior bit error rate (BER) resilience showing ∼94% training and 88% inference accuracy with 1% BER.
UR - http://www.scopus.com/inward/record.url?scp=85153722628&partnerID=8YFLogxK
U2 - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134180
DO - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134180
M3 - Conference contribution
AN - SCOPUS:85153722628
T3 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
BT - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Y2 - 17 April 2023 through 20 April 2023
ER -