Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology

Yun Yan Chung; Jia Min Shieh; Sheng Kai Su; Hung Li Chiang; Tzu Chiang Chen; Lain Jong Li; H. S.Philip Wong; Wen-Bin Jian; Chao-Hsin Chien; Kuan Cheng Lu; Chao Ching Cheng; Ming Yang Li; Chao Ting Lin; Chi Feng Li; Jyun Hong Chen; Tung Yen Lai; Kai Shin Li

doi:10.1109/TED.2019.2946101

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS₂ Channel Directly Grown on SiO_x/Si Substrates Using Area-Selective CVD Technology

Yun Yan Chung, Jia Min Shieh, Sheng Kai Su, Hung Li Chiang, Tzu Chiang Chen, Lain Jong Li, H. S.Philip Wong, Wen-Bin Jian, Chao-Hsin Chien^*, Kuan Cheng Lu, Chao Ching Cheng, Ming Yang Li, Chao Ting Lin, Chi Feng Li, Jyun Hong Chen, Tung Yen Lai, Kai Shin Li

^*Corresponding author for this work

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS₂ film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS₂ channels on SiO_x/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10⁶, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).

Original language	English
Article number	8889483
Pages (from-to)	5381-5386
Number of pages	6
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	12
DOIs	https://doi.org/10.1109/TED.2019.2946101
State	Published - Dec 2019

Keywords

Area selective chemical reaction deposition (CVD)
p-MOSFET
short channel device
tungsten disulfide
WS2

Access to Document

10.1109/TED.2019.2946101

Cite this

Chung, Y. Y., Shieh, J. M., Su, S. K., Chiang, H. L., Chen, T. C., Li, L. J., Wong, H. S. P., Jian, W.-B., Chien, C.-H., Lu, K. C., Cheng, C. C., Li, M. Y., Lin, C. T., Li, C. F., Chen, J. H., Lai, T. Y., & Li, K. S. (2019). Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS₂ Channel Directly Grown on SiO_x/Si Substrates Using Area-Selective CVD Technology. IEEE Transactions on Electron Devices, 66(12), 5381-5386. Article 8889483. https://doi.org/10.1109/TED.2019.2946101

@article{83075a97450b4d6b982fa6bad511f38b,

title = "Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology",

abstract = "For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).",

keywords = "Area selective chemical reaction deposition (CVD), p-MOSFET, short channel device, tungsten disulfide, WS2",

author = "Chung, {Yun Yan} and Shieh, {Jia Min} and Su, {Sheng Kai} and Chiang, {Hung Li} and Chen, {Tzu Chiang} and Li, {Lain Jong} and Wong, {H. S.Philip} and Wen-Bin Jian and Chao-Hsin Chien and Lu, {Kuan Cheng} and Cheng, {Chao Ching} and Li, {Ming Yang} and Lin, {Chao Ting} and Li, {Chi Feng} and Chen, {Jyun Hong} and Lai, {Tung Yen} and Li, {Kai Shin}",

year = "2019",

month = dec,

doi = "10.1109/TED.2019.2946101",

language = "English",

volume = "66",

pages = "5381--5386",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "12",

}

Chung, YY, Shieh, JM, Su, SK, Chiang, HL, Chen, TC, Li, LJ, Wong, HSP, Jian, W-B , Chien, C-H, Lu, KC, Cheng, CC, Li, MY, Lin, CT, Li, CF, Chen, JH, Lai, TY & Li, KS 2019, 'Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS₂ Channel Directly Grown on SiO_x/Si Substrates Using Area-Selective CVD Technology', IEEE Transactions on Electron Devices, vol. 66, no. 12, 8889483, pp. 5381-5386. https://doi.org/10.1109/TED.2019.2946101

TY - JOUR

T1 - Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology

AU - Chung, Yun Yan

AU - Shieh, Jia Min

AU - Su, Sheng Kai

AU - Chiang, Hung Li

AU - Chen, Tzu Chiang

AU - Li, Lain Jong

AU - Wong, H. S.Philip

AU - Jian, Wen-Bin

AU - Chien, Chao-Hsin

AU - Lu, Kuan Cheng

AU - Cheng, Chao Ching

AU - Li, Ming Yang

AU - Lin, Chao Ting

AU - Li, Chi Feng

AU - Chen, Jyun Hong

AU - Lai, Tung Yen

AU - Li, Kai Shin

PY - 2019/12

Y1 - 2019/12

N2 - For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).

AB - For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).

KW - Area selective chemical reaction deposition (CVD)

KW - p-MOSFET

KW - short channel device

KW - tungsten disulfide

KW - WS2

UR - http://www.scopus.com/inward/record.url?scp=85076082931&partnerID=8YFLogxK

U2 - 10.1109/TED.2019.2946101

DO - 10.1109/TED.2019.2946101

M3 - Article

AN - SCOPUS:85076082931

SN - 0018-9383

VL - 66

SP - 5381

EP - 5386

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 12

M1 - 8889483

ER -

Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS₂ Channel Directly Grown on SiO_x/Si Substrates Using Area-Selective CVD Technology

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this